linux/drivers/clk/socfpga/clk-pll-s10.c

// SPDX-License-Identifier: GPL-2.0
/*
 * Copyright (C) 2017, Intel Corporation
 */
#include <linux/slab.h>
#include <linux/clk-provider.h>
#include <linux/io.h>

#include "stratix10-clk.h"
#include "clk.h"

/* Clock Manager offsets */
#define CLK_MGR_PLL_CLK_SRC_SHIFT …
#define CLK_MGR_PLL_CLK_SRC_MASK …

/* PLL Clock enable bits */
#define SOCFPGA_PLL_POWER …
#define SOCFPGA_PLL_RESET_MASK …
#define SOCFPGA_PLL_REFDIV_MASK …
#define SOCFPGA_PLL_REFDIV_SHIFT …
#define SOCFPGA_PLL_AREFDIV_MASK …
#define SOCFPGA_PLL_DREFDIV_MASK …
#define SOCFPGA_PLL_DREFDIV_SHIFT …
#define SOCFPGA_PLL_MDIV_MASK …
#define SOCFPGA_PLL_MDIV_SHIFT …
#define SOCFPGA_AGILEX_PLL_MDIV_MASK …
#define SWCTRLBTCLKSEL_MASK …
#define SWCTRLBTCLKSEL_SHIFT …

#define SOCFPGA_N5X_PLLDIV_FDIV_MASK …
#define SOCFPGA_N5X_PLLDIV_FDIV_SHIFT …
#define SOCFPGA_N5X_PLLDIV_RDIV_MASK …
#define SOCFPGA_N5X_PLLDIV_QDIV_MASK …
#define SOCFPGA_N5X_PLLDIV_QDIV_SHIFT …

#define SOCFPGA_BOOT_CLK …

#define to_socfpga_clk(p) …

static unsigned long n5x_clk_pll_recalc_rate(struct clk_hw *hwclk,
						unsigned long parent_rate)
{ … }

static unsigned long agilex_clk_pll_recalc_rate(struct clk_hw *hwclk,
						unsigned long parent_rate)
{ … }

static unsigned long clk_pll_recalc_rate(struct clk_hw *hwclk,
					 unsigned long parent_rate)
{ … }

static unsigned long clk_boot_clk_recalc_rate(struct clk_hw *hwclk,
					 unsigned long parent_rate)
{ … }


static u8 clk_pll_get_parent(struct clk_hw *hwclk)
{ … }

static u8 clk_boot_get_parent(struct clk_hw *hwclk)
{ … }

static int clk_pll_prepare(struct clk_hw *hwclk)
{ … }

static int n5x_clk_pll_prepare(struct clk_hw *hwclk)
{ … }

static const struct clk_ops n5x_clk_pll_ops = …;

static const struct clk_ops agilex_clk_pll_ops = …;

static const struct clk_ops clk_pll_ops = …;

static const struct clk_ops clk_boot_ops = …;

struct clk_hw *s10_register_pll(const struct stratix10_pll_clock *clks,
			     void __iomem *reg)
{ … }

struct clk_hw *agilex_register_pll(const struct stratix10_pll_clock *clks,
				void __iomem *reg)
{ … }

struct clk_hw *n5x_register_pll(const struct stratix10_pll_clock *clks,
			     void __iomem *reg)
{ … }