linux/drivers/clk/socfpga/clk-gate-s10.c

// SPDX-License-Identifier: GPL-2.0
/*
 * Copyright (C) 2017, Intel Corporation
 */
#include <linux/clk-provider.h>
#include <linux/io.h>
#include <linux/slab.h>
#include "stratix10-clk.h"
#include "clk.h"

#define SOCFPGA_CS_PDBG_CLK …
#define to_socfpga_gate_clk(p) …

#define SOCFPGA_EMAC0_CLK …
#define SOCFPGA_EMAC1_CLK …
#define SOCFPGA_EMAC2_CLK …
#define AGILEX_BYPASS_OFFSET …
#define STRATIX10_BYPASS_OFFSET …
#define BOOTCLK_BYPASS …

static unsigned long socfpga_gate_clk_recalc_rate(struct clk_hw *hwclk,
						  unsigned long parent_rate)
{ … }

static unsigned long socfpga_dbg_clk_recalc_rate(struct clk_hw *hwclk,
						  unsigned long parent_rate)
{ … }

static u8 socfpga_gate_get_parent(struct clk_hw *hwclk)
{ … }

static u8 socfpga_agilex_gate_get_parent(struct clk_hw *hwclk)
{ … }

static struct clk_ops gateclk_ops = …;

static const struct clk_ops agilex_gateclk_ops = …;

static const struct clk_ops dbgclk_ops = …;

struct clk_hw *s10_register_gate(const struct stratix10_gate_clock *clks, void __iomem *regbase)
{ … }

struct clk_hw *agilex_register_gate(const struct stratix10_gate_clock *clks, void __iomem *regbase)
{ … }