linux/include/dt-bindings/clock/sprd,sc9860-clk.h

// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
//
// Spreadtrum SC9860 platform clocks
//
// Copyright (C) 2017, Spreadtrum Communications Inc.

#ifndef _DT_BINDINGS_CLK_SC9860_H_
#define _DT_BINDINGS_CLK_SC9860_H_

#define CLK_FAC_4M
#define CLK_FAC_2M
#define CLK_FAC_1M
#define CLK_FAC_250K
#define CLK_FAC_RPLL0_26M
#define CLK_FAC_RPLL1_26M
#define CLK_FAC_RCO25M
#define CLK_FAC_RCO4M
#define CLK_FAC_RCO2M
#define CLK_FAC_3K2
#define CLK_FAC_1K
#define CLK_MPLL0_GATE
#define CLK_MPLL1_GATE
#define CLK_DPLL0_GATE
#define CLK_DPLL1_GATE
#define CLK_LTEPLL0_GATE
#define CLK_TWPLL_GATE
#define CLK_LTEPLL1_GATE
#define CLK_RPLL0_GATE
#define CLK_RPLL1_GATE
#define CLK_CPPLL_GATE
#define CLK_GPLL_GATE
#define CLK_PMU_GATE_NUM

#define CLK_MPLL0
#define CLK_MPLL1
#define CLK_DPLL0
#define CLK_DPLL1
#define CLK_RPLL0
#define CLK_RPLL1
#define CLK_TWPLL
#define CLK_LTEPLL0
#define CLK_LTEPLL1
#define CLK_GPLL
#define CLK_CPPLL
#define CLK_GPLL_42M5
#define CLK_TWPLL_768M
#define CLK_TWPLL_384M
#define CLK_TWPLL_192M
#define CLK_TWPLL_96M
#define CLK_TWPLL_48M
#define CLK_TWPLL_24M
#define CLK_TWPLL_12M
#define CLK_TWPLL_512M
#define CLK_TWPLL_256M
#define CLK_TWPLL_128M
#define CLK_TWPLL_64M
#define CLK_TWPLL_307M2
#define CLK_TWPLL_153M6
#define CLK_TWPLL_76M8
#define CLK_TWPLL_51M2
#define CLK_TWPLL_38M4
#define CLK_TWPLL_19M2
#define CLK_L0_614M4
#define CLK_L0_409M6
#define CLK_L0_38M
#define CLK_L1_38M
#define CLK_RPLL0_192M
#define CLK_RPLL0_96M
#define CLK_RPLL0_48M
#define CLK_RPLL1_468M
#define CLK_RPLL1_192M
#define CLK_RPLL1_96M
#define CLK_RPLL1_64M
#define CLK_RPLL1_48M
#define CLK_DPLL0_50M
#define CLK_DPLL1_50M
#define CLK_CPPLL_50M
#define CLK_M0_39M
#define CLK_M1_63M
#define CLK_PLL_NUM


#define CLK_AP_APB
#define CLK_AP_USB3
#define CLK_UART0
#define CLK_UART1
#define CLK_UART2
#define CLK_UART3
#define CLK_UART4
#define CLK_I2C0
#define CLK_I2C1
#define CLK_I2C2
#define CLK_I2C3
#define CLK_I2C4
#define CLK_I2C5
#define CLK_SPI0
#define CLK_SPI1
#define CLK_SPI2
#define CLK_SPI3
#define CLK_IIS0
#define CLK_IIS1
#define CLK_IIS2
#define CLK_IIS3
#define CLK_AP_CLK_NUM

#define CLK_AON_APB
#define CLK_AUX0
#define CLK_AUX1
#define CLK_AUX2
#define CLK_PROBE
#define CLK_SP_AHB
#define CLK_CCI
#define CLK_GIC
#define CLK_CSSYS
#define CLK_SDIO0_2X
#define CLK_SDIO1_2X
#define CLK_SDIO2_2X
#define CLK_EMMC_2X
#define CLK_SDIO0_1X
#define CLK_SDIO1_1X
#define CLK_SDIO2_1X
#define CLK_EMMC_1X
#define CLK_ADI
#define CLK_PWM0
#define CLK_PWM1
#define CLK_PWM2
#define CLK_PWM3
#define CLK_EFUSE
#define CLK_CM3_UART0
#define CLK_CM3_UART1
#define CLK_THM
#define CLK_CM3_I2C0
#define CLK_CM3_I2C1
#define CLK_CM4_SPI
#define CLK_AON_I2C
#define CLK_AVS
#define CLK_CA53_DAP
#define CLK_CA53_TS
#define CLK_DJTAG_TCK
#define CLK_PMU
#define CLK_PMU_26M
#define CLK_DEBOUNCE
#define CLK_OTG2_REF
#define CLK_USB3_REF
#define CLK_AP_AXI
#define CLK_AON_PREDIV_NUM

#define CLK_USB3_EB
#define CLK_USB3_SUSPEND_EB
#define CLK_USB3_REF_EB
#define CLK_DMA_EB
#define CLK_SDIO0_EB
#define CLK_SDIO1_EB
#define CLK_SDIO2_EB
#define CLK_EMMC_EB
#define CLK_ROM_EB
#define CLK_BUSMON_EB
#define CLK_CC63S_EB
#define CLK_CC63P_EB
#define CLK_CE0_EB
#define CLK_CE1_EB
#define CLK_APAHB_GATE_NUM

#define CLK_AVS_LIT_EB
#define CLK_AVS_BIG_EB
#define CLK_AP_INTC5_EB
#define CLK_GPIO_EB
#define CLK_PWM0_EB
#define CLK_PWM1_EB
#define CLK_PWM2_EB
#define CLK_PWM3_EB
#define CLK_KPD_EB
#define CLK_AON_SYS_EB
#define CLK_AP_SYS_EB
#define CLK_AON_TMR_EB
#define CLK_AP_TMR0_EB
#define CLK_EFUSE_EB
#define CLK_EIC_EB
#define CLK_PUB1_REG_EB
#define CLK_ADI_EB
#define CLK_AP_INTC0_EB
#define CLK_AP_INTC1_EB
#define CLK_AP_INTC2_EB
#define CLK_AP_INTC3_EB
#define CLK_AP_INTC4_EB
#define CLK_SPLK_EB
#define CLK_MSPI_EB
#define CLK_PUB0_REG_EB
#define CLK_PIN_EB
#define CLK_AON_CKG_EB
#define CLK_GPU_EB
#define CLK_APCPU_TS0_EB
#define CLK_APCPU_TS1_EB
#define CLK_DAP_EB
#define CLK_I2C_EB
#define CLK_PMU_EB
#define CLK_THM_EB
#define CLK_AUX0_EB
#define CLK_AUX1_EB
#define CLK_AUX2_EB
#define CLK_PROBE_EB
#define CLK_GPU0_AVS_EB
#define CLK_GPU1_AVS_EB
#define CLK_APCPU_WDG_EB
#define CLK_AP_TMR1_EB
#define CLK_AP_TMR2_EB
#define CLK_DISP_EMC_EB
#define CLK_ZIP_EMC_EB
#define CLK_GSP_EMC_EB
#define CLK_OSC_AON_EB
#define CLK_LVDS_TRX_EB
#define CLK_LVDS_TCXO_EB
#define CLK_MDAR_EB
#define CLK_RTC4M0_CAL_EB
#define CLK_RCT100M_CAL_EB
#define CLK_DJTAG_EB
#define CLK_MBOX_EB
#define CLK_AON_DMA_EB
#define CLK_DBG_EMC_EB
#define CLK_LVDS_PLL_DIV_EN
#define CLK_DEF_EB
#define CLK_AON_APB_RSV0
#define CLK_ORP_JTAG_EB
#define CLK_VSP_EB
#define CLK_CAM_EB
#define CLK_DISP_EB
#define CLK_DBG_AXI_IF_EB
#define CLK_SDIO0_2X_EN
#define CLK_SDIO1_2X_EN
#define CLK_SDIO2_2X_EN
#define CLK_EMMC_2X_EN
#define CLK_ARCH_RTC_EB
#define CLK_KPB_RTC_EB
#define CLK_AON_SYST_RTC_EB
#define CLK_AP_SYST_RTC_EB
#define CLK_AON_TMR_RTC_EB
#define CLK_AP_TMR0_RTC_EB
#define CLK_EIC_RTC_EB
#define CLK_EIC_RTCDV5_EB
#define CLK_AP_WDG_RTC_EB
#define CLK_AP_TMR1_RTC_EB
#define CLK_AP_TMR2_RTC_EB
#define CLK_DCXO_TMR_RTC_EB
#define CLK_BB_CAL_RTC_EB
#define CLK_AVS_BIG_RTC_EB
#define CLK_AVS_LIT_RTC_EB
#define CLK_AVS_GPU0_RTC_EB
#define CLK_AVS_GPU1_RTC_EB
#define CLK_GPU_TS_EB
#define CLK_RTCDV10_EB
#define CLK_AON_GATE_NUM

#define CLK_LIT_MCU
#define CLK_BIG_MCU
#define CLK_AONSECURE_NUM

#define CLK_AGCP_IIS0_EB
#define CLK_AGCP_IIS1_EB
#define CLK_AGCP_IIS2_EB
#define CLK_AGCP_IIS3_EB
#define CLK_AGCP_UART_EB
#define CLK_AGCP_DMACP_EB
#define CLK_AGCP_DMAAP_EB
#define CLK_AGCP_ARC48K_EB
#define CLK_AGCP_SRC44P1K_EB
#define CLK_AGCP_MCDT_EB
#define CLK_AGCP_VBCIFD_EB
#define CLK_AGCP_VBC_EB
#define CLK_AGCP_SPINLOCK_EB
#define CLK_AGCP_ICU_EB
#define CLK_AGCP_AP_ASHB_EB
#define CLK_AGCP_CP_ASHB_EB
#define CLK_AGCP_AUD_EB
#define CLK_AGCP_AUDIF_EB
#define CLK_AGCP_GATE_NUM

#define CLK_GPU
#define CLK_GPU_NUM

#define CLK_AHB_VSP
#define CLK_VSP
#define CLK_VSP_ENC
#define CLK_VPP
#define CLK_VSP_26M
#define CLK_VSP_NUM

#define CLK_VSP_DEC_EB
#define CLK_VSP_CKG_EB
#define CLK_VSP_MMU_EB
#define CLK_VSP_ENC_EB
#define CLK_VPP_EB
#define CLK_VSP_26M_EB
#define CLK_VSP_AXI_GATE
#define CLK_VSP_ENC_GATE
#define CLK_VPP_AXI_GATE
#define CLK_VSP_BM_GATE
#define CLK_VSP_ENC_BM_GATE
#define CLK_VPP_BM_GATE
#define CLK_VSP_GATE_NUM

#define CLK_AHB_CAM
#define CLK_SENSOR0
#define CLK_SENSOR1
#define CLK_SENSOR2
#define CLK_MIPI_CSI0_EB
#define CLK_MIPI_CSI1_EB
#define CLK_CAM_NUM

#define CLK_DCAM0_EB
#define CLK_DCAM1_EB
#define CLK_ISP0_EB
#define CLK_CSI0_EB
#define CLK_CSI1_EB
#define CLK_JPG0_EB
#define CLK_JPG1_EB
#define CLK_CAM_CKG_EB
#define CLK_CAM_MMU_EB
#define CLK_ISP1_EB
#define CLK_CPP_EB
#define CLK_MMU_PF_EB
#define CLK_ISP2_EB
#define CLK_DCAM2ISP_IF_EB
#define CLK_ISP2DCAM_IF_EB
#define CLK_ISP_LCLK_EB
#define CLK_ISP_ICLK_EB
#define CLK_ISP_MCLK_EB
#define CLK_ISP_PCLK_EB
#define CLK_ISP_ISP2DCAM_EB
#define CLK_DCAM0_IF_EB
#define CLK_CLK26M_IF_EB
#define CLK_CPHY0_GATE
#define CLK_MIPI_CSI0_GATE
#define CLK_CPHY1_GATE
#define CLK_MIPI_CSI1
#define CLK_DCAM0_AXI_GATE
#define CLK_DCAM1_AXI_GATE
#define CLK_SENSOR0_GATE
#define CLK_SENSOR1_GATE
#define CLK_JPG0_AXI_GATE
#define CLK_GPG1_AXI_GATE
#define CLK_ISP0_AXI_GATE
#define CLK_ISP1_AXI_GATE
#define CLK_ISP2_AXI_GATE
#define CLK_CPP_AXI_GATE
#define CLK_D0_IF_AXI_GATE
#define CLK_D2I_IF_AXI_GATE
#define CLK_I2D_IF_AXI_GATE
#define CLK_SPARE_AXI_GATE
#define CLK_SENSOR2_GATE
#define CLK_D0IF_IN_D_EN
#define CLK_D1IF_IN_D_EN
#define CLK_D0IF_IN_D2I_EN
#define CLK_D1IF_IN_D2I_EN
#define CLK_IA_IN_D2I_EN
#define CLK_IB_IN_D2I_EN
#define CLK_IC_IN_D2I_EN
#define CLK_IA_IN_I_EN
#define CLK_IB_IN_I_EN
#define CLK_IC_IN_I_EN
#define CLK_CAM_GATE_NUM

#define CLK_AHB_DISP
#define CLK_DISPC0_DPI
#define CLK_DISPC1_DPI
#define CLK_DISP_NUM

#define CLK_DISPC0_EB
#define CLK_DISPC1_EB
#define CLK_DISPC_MMU_EB
#define CLK_GSP0_EB
#define CLK_GSP1_EB
#define CLK_GSP0_MMU_EB
#define CLK_GSP1_MMU_EB
#define CLK_DSI0_EB
#define CLK_DSI1_EB
#define CLK_DISP_CKG_EB
#define CLK_DISP_GPU_EB
#define CLK_GPU_MTX_EB
#define CLK_GSP_MTX_EB
#define CLK_TMC_MTX_EB
#define CLK_DISPC_MTX_EB
#define CLK_DPHY0_GATE
#define CLK_DPHY1_GATE
#define CLK_GSP0_A_GATE
#define CLK_GSP1_A_GATE
#define CLK_GSP0_F_GATE
#define CLK_GSP1_F_GATE
#define CLK_D_MTX_F_GATE
#define CLK_D_MTX_A_GATE
#define CLK_D_NOC_F_GATE
#define CLK_D_NOC_A_GATE
#define CLK_GSP_MTX_F_GATE
#define CLK_GSP_MTX_A_GATE
#define CLK_GSP_NOC_F_GATE
#define CLK_GSP_NOC_A_GATE
#define CLK_DISPM0IDLE_GATE
#define CLK_GSPM0IDLE_GATE
#define CLK_DISP_GATE_NUM

#define CLK_SIM0_EB
#define CLK_IIS0_EB
#define CLK_IIS1_EB
#define CLK_IIS2_EB
#define CLK_IIS3_EB
#define CLK_SPI0_EB
#define CLK_SPI1_EB
#define CLK_SPI2_EB
#define CLK_I2C0_EB
#define CLK_I2C1_EB
#define CLK_I2C2_EB
#define CLK_I2C3_EB
#define CLK_I2C4_EB
#define CLK_I2C5_EB
#define CLK_UART0_EB
#define CLK_UART1_EB
#define CLK_UART2_EB
#define CLK_UART3_EB
#define CLK_UART4_EB
#define CLK_AP_CKG_EB
#define CLK_SPI3_EB
#define CLK_APAPB_GATE_NUM

#endif /* _DT_BINDINGS_CLK_SC9860_H_ */