/* SPDX-License-Identifier: GPL-2.0 */ #ifndef __CLK_STARFIVE_JH71X0_H #define __CLK_STARFIVE_JH71X0_H #include <linux/bits.h> #include <linux/clk-provider.h> #include <linux/device.h> #include <linux/spinlock.h> /* register fields */ #define JH71X0_CLK_ENABLE … #define JH71X0_CLK_INVERT … #define JH71X0_CLK_MUX_MASK … #define JH71X0_CLK_MUX_SHIFT … #define JH71X0_CLK_DIV_MASK … #define JH71X0_CLK_FRAC_MASK … #define JH71X0_CLK_FRAC_SHIFT … #define JH71X0_CLK_INT_MASK … /* fractional divider min/max */ #define JH71X0_CLK_FRAC_MIN … #define JH71X0_CLK_FRAC_MAX … /* clock data */ struct jh71x0_clk_data { … }; #define JH71X0_GATE(_idx, _name, _flags, _parent) … #define JH71X0__DIV(_idx, _name, _max, _parent) … #define JH71X0_GDIV(_idx, _name, _flags, _max, _parent) … #define JH71X0_FDIV(_idx, _name, _parent) … #define JH71X0__MUX(_idx, _name, _flags, _nparents, ...) … #define JH71X0_GMUX(_idx, _name, _flags, _nparents, ...) … #define JH71X0_MDIV(_idx, _name, _max, _nparents, ...) … #define JH71X0__GMD(_idx, _name, _flags, _max, _nparents, ...) … #define JH71X0__INV(_idx, _name, _parent) … struct jh71x0_clk { … }; struct jh71x0_clk_priv { … }; const struct clk_ops *starfive_jh71x0_clk_ops(u32 max); #endif
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