// SPDX-License-Identifier: GPL-2.0 /* * StarFive JH7110 PLL Clock Generator Driver * * Copyright (C) 2023 StarFive Technology Co., Ltd. * Copyright (C) 2023 Emil Renner Berthing <[email protected]> * * This driver is about to register JH7110 PLL clock generator and support ops. * The JH7110 have three PLL clock, PLL0, PLL1 and PLL2. * Each PLL clocks work in integer mode or fraction mode by some dividers, * and the configuration registers and dividers are set in several syscon registers. * The formula for calculating frequency is: * Fvco = Fref * (NI + NF) / M / Q1 * Fref: OSC source clock rate * NI: integer frequency dividing ratio of feedback divider, set by fbdiv[11:0]. * NF: fractional frequency dividing ratio, set by frac[23:0]. NF = frac[23:0] / 2^24 = 0 ~ 0.999. * M: frequency dividing ratio of pre-divider, set by prediv[5:0]. * Q1: frequency dividing ratio of post divider, set by 2^postdiv1[1:0], eg. 1, 2, 4 or 8. */ #include <linux/bits.h> #include <linux/clk-provider.h> #include <linux/debugfs.h> #include <linux/device.h> #include <linux/kernel.h> #include <linux/mfd/syscon.h> #include <linux/platform_device.h> #include <linux/regmap.h> #include <dt-bindings/clock/starfive,jh7110-crg.h> /* this driver expects a 24MHz input frequency from the oscillator */ #define JH7110_PLL_OSC_RATE … #define JH7110_PLL0_PD_OFFSET … #define JH7110_PLL0_DACPD_SHIFT … #define JH7110_PLL0_DACPD_MASK … #define JH7110_PLL0_DSMPD_SHIFT … #define JH7110_PLL0_DSMPD_MASK … #define JH7110_PLL0_FBDIV_OFFSET … #define JH7110_PLL0_FBDIV_SHIFT … #define JH7110_PLL0_FBDIV_MASK … #define JH7110_PLL0_FRAC_OFFSET … #define JH7110_PLL0_PREDIV_OFFSET … #define JH7110_PLL1_PD_OFFSET … #define JH7110_PLL1_DACPD_SHIFT … #define JH7110_PLL1_DACPD_MASK … #define JH7110_PLL1_DSMPD_SHIFT … #define JH7110_PLL1_DSMPD_MASK … #define JH7110_PLL1_FBDIV_OFFSET … #define JH7110_PLL1_FBDIV_SHIFT … #define JH7110_PLL1_FBDIV_MASK … #define JH7110_PLL1_FRAC_OFFSET … #define JH7110_PLL1_PREDIV_OFFSET … #define JH7110_PLL2_PD_OFFSET … #define JH7110_PLL2_DACPD_SHIFT … #define JH7110_PLL2_DACPD_MASK … #define JH7110_PLL2_DSMPD_SHIFT … #define JH7110_PLL2_DSMPD_MASK … #define JH7110_PLL2_FBDIV_OFFSET … #define JH7110_PLL2_FBDIV_SHIFT … #define JH7110_PLL2_FBDIV_MASK … #define JH7110_PLL2_FRAC_OFFSET … #define JH7110_PLL2_PREDIV_OFFSET … #define JH7110_PLL_FRAC_SHIFT … #define JH7110_PLL_FRAC_MASK … #define JH7110_PLL_POSTDIV1_SHIFT … #define JH7110_PLL_POSTDIV1_MASK … #define JH7110_PLL_PREDIV_SHIFT … #define JH7110_PLL_PREDIV_MASK … enum jh7110_pll_mode { … }; struct jh7110_pll_preset { … }; struct jh7110_pll_info { … }; #define _JH7110_PLL(_idx, _name, _presets) … #define JH7110_PLL(idx, name, presets) … struct jh7110_pll_data { … }; struct jh7110_pll_priv { … }; struct jh7110_pll_regvals { … }; /* * Because the pll frequency is relatively fixed, * it cannot be set arbitrarily, so it needs a specific configuration. * PLL0 frequency should be multiple of 125MHz (USB frequency). */ static const struct jh7110_pll_preset jh7110_pll0_presets[] = …; static const struct jh7110_pll_preset jh7110_pll1_presets[] = …; static const struct jh7110_pll_preset jh7110_pll2_presets[] = …; static const struct jh7110_pll_info jh7110_plls[JH7110_PLLCLK_END] = …; static struct jh7110_pll_data *jh7110_pll_data_from(struct clk_hw *hw) { … } static struct jh7110_pll_priv *jh7110_pll_priv_from(struct jh7110_pll_data *pll) { … } static void jh7110_pll_regvals_get(struct regmap *regmap, const struct jh7110_pll_info *info, struct jh7110_pll_regvals *ret) { … } static unsigned long jh7110_pll_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) { … } static int jh7110_pll_determine_rate(struct clk_hw *hw, struct clk_rate_request *req) { … } static int jh7110_pll_set_rate(struct clk_hw *hw, unsigned long rate, unsigned long parent_rate) { … } #ifdef CONFIG_DEBUG_FS static int jh7110_pll_registers_read(struct seq_file *s, void *unused) { … } static int jh7110_pll_registers_open(struct inode *inode, struct file *f) { … } static const struct file_operations jh7110_pll_registers_ops = …; static void jh7110_pll_debug_init(struct clk_hw *hw, struct dentry *dentry) { … } #else #define jh7110_pll_debug_init … #endif static const struct clk_ops jh7110_pll_ops = …; static struct clk_hw *jh7110_pll_get(struct of_phandle_args *clkspec, void *data) { … } static int jh7110_pll_probe(struct platform_device *pdev) { … } static const struct of_device_id jh7110_pll_match[] = …; MODULE_DEVICE_TABLE(of, jh7110_pll_match); static struct platform_driver jh7110_pll_driver = …; builtin_platform_driver_probe(…);
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