/* SPDX-License-Identifier: GPL-2.0+ */ /* * Copyright 2017 Icenowy Zheng <[email protected]> * */ #ifndef _CCU_SUNIV_F1C100S_H_ #define _CCU_SUNIV_F1C100S_H_ #include <dt-bindings/clock/suniv-ccu-f1c100s.h> #include <dt-bindings/reset/suniv-ccu-f1c100s.h> #define CLK_PLL_CPU … #define CLK_PLL_AUDIO_BASE … #define CLK_PLL_AUDIO … #define CLK_PLL_AUDIO_2X … #define CLK_PLL_AUDIO_4X … #define CLK_PLL_AUDIO_8X … #define CLK_PLL_VIDEO … #define CLK_PLL_VIDEO_2X … #define CLK_PLL_VE … #define CLK_PLL_DDR0 … #define CLK_PLL_PERIPH … /* CPU clock is exported */ #define CLK_AHB … #define CLK_APB … /* All bus gates, DRAM gates and mod clocks are exported */ #define CLK_NUMBER … #endif /* _CCU_SUNIV_F1C100S_H_ */
Codebase Browser
linux