// SPDX-License-Identifier: GPL-2.0-only /* * Copyright (c) 2016 Maxime Ripard. All rights reserved. */ #include <linux/clk-provider.h> #include <linux/io.h> #include <linux/module.h> #include <linux/platform_device.h> #include "ccu_common.h" #include "ccu_reset.h" #include "ccu_div.h" #include "ccu_gate.h" #include "ccu_mp.h" #include "ccu_mult.h" #include "ccu_nk.h" #include "ccu_nkm.h" #include "ccu_nkmp.h" #include "ccu_nm.h" #include "ccu_phase.h" #include "ccu-sun50i-a64.h" static struct ccu_nkmp pll_cpux_clk = …; /* * The Audio PLL is supposed to have 4 outputs: 3 fixed factors from * the base (2x, 4x and 8x), and one variable divider (the one true * pll audio). * * With sigma-delta modulation for fractional-N on the audio PLL, * we have to use specific dividers. This means the variable divider * can no longer be used, as the audio codec requests the exact clock * rates we support through this mechanism. So we now hard code the * variable divider to 1. This means the clock rates will no longer * match the clock names. */ #define SUN50I_A64_PLL_AUDIO_REG … static struct ccu_sdm_setting pll_audio_sdm_table[] = …; static SUNXI_CCU_NM_WITH_SDM_GATE_LOCK(pll_audio_base_clk, "pll-audio-base", "osc24M", 0x008, 8, 7, /* N */ 0, 5, /* M */ pll_audio_sdm_table, BIT(24), 0x284, BIT(31), BIT(31), /* gate */ BIT(28), /* lock */ CLK_SET_RATE_UNGATE); static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK_MIN_MAX_CLOSEST(pll_video0_clk, "pll-video0", "osc24M", 0x010, 192000000, /* Minimum rate */ 1008000000, /* Maximum rate */ 8, 7, /* N */ 0, 4, /* M */ BIT(24), /* frac enable */ BIT(25), /* frac select */ 270000000, /* frac rate 0 */ 297000000, /* frac rate 1 */ BIT(31), /* gate */ BIT(28), /* lock */ CLK_SET_RATE_UNGATE); static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_ve_clk, "pll-ve", "osc24M", 0x018, 8, 7, /* N */ 0, 4, /* M */ BIT(24), /* frac enable */ BIT(25), /* frac select */ 270000000, /* frac rate 0 */ 297000000, /* frac rate 1 */ BIT(31), /* gate */ BIT(28), /* lock */ CLK_SET_RATE_UNGATE); static SUNXI_CCU_NKM_WITH_GATE_LOCK(pll_ddr0_clk, "pll-ddr0", "osc24M", 0x020, 8, 5, /* N */ 4, 2, /* K */ 0, 2, /* M */ BIT(31), /* gate */ BIT(28), /* lock */ CLK_SET_RATE_UNGATE); static struct ccu_nk pll_periph0_clk = …; static struct ccu_nk pll_periph1_clk = …; static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK_MIN_MAX(pll_video1_clk, "pll-video1", "osc24M", 0x030, 192000000, /* Minimum rate */ 1008000000, /* Maximum rate */ 8, 7, /* N */ 0, 4, /* M */ BIT(24), /* frac enable */ BIT(25), /* frac select */ 270000000, /* frac rate 0 */ 297000000, /* frac rate 1 */ BIT(31), /* gate */ BIT(28), /* lock */ CLK_SET_RATE_UNGATE); static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_gpu_clk, "pll-gpu", "osc24M", 0x038, 8, 7, /* N */ 0, 4, /* M */ BIT(24), /* frac enable */ BIT(25), /* frac select */ 270000000, /* frac rate 0 */ 297000000, /* frac rate 1 */ BIT(31), /* gate */ BIT(28), /* lock */ CLK_SET_RATE_UNGATE); /* * The output function can be changed to something more complex that * we do not handle yet. * * Hardcode the mode so that we don't fall in that case. */ #define SUN50I_A64_PLL_MIPI_REG … static struct ccu_nkm pll_mipi_clk = …; static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_hsic_clk, "pll-hsic", "osc24M", 0x044, 8, 7, /* N */ 0, 4, /* M */ BIT(24), /* frac enable */ BIT(25), /* frac select */ 270000000, /* frac rate 0 */ 297000000, /* frac rate 1 */ BIT(31), /* gate */ BIT(28), /* lock */ CLK_SET_RATE_UNGATE); static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_de_clk, "pll-de", "osc24M", 0x048, 8, 7, /* N */ 0, 4, /* M */ BIT(24), /* frac enable */ BIT(25), /* frac select */ 270000000, /* frac rate 0 */ 297000000, /* frac rate 1 */ BIT(31), /* gate */ BIT(28), /* lock */ CLK_SET_RATE_UNGATE); static SUNXI_CCU_NM_WITH_GATE_LOCK(pll_ddr1_clk, "pll-ddr1", "osc24M", 0x04c, 8, 7, /* N */ 0, 2, /* M */ BIT(31), /* gate */ BIT(28), /* lock */ CLK_SET_RATE_UNGATE); static const char * const cpux_parents[] = …; static SUNXI_CCU_MUX(cpux_clk, "cpux", cpux_parents, 0x050, 16, 2, CLK_SET_RATE_PARENT | CLK_IS_CRITICAL); static SUNXI_CCU_M(axi_clk, "axi", "cpux", 0x050, 0, 2, 0); static const char * const ahb1_parents[] = …; static const struct ccu_mux_var_prediv ahb1_predivs[] = …; static struct ccu_div ahb1_clk = …; static struct clk_div_table apb1_div_table[] = …; static SUNXI_CCU_DIV_TABLE(apb1_clk, "apb1", "ahb1", 0x054, 8, 2, apb1_div_table, 0); static const char * const apb2_parents[] = …; static SUNXI_CCU_MP_WITH_MUX(apb2_clk, "apb2", apb2_parents, 0x058, 0, 5, /* M */ 16, 2, /* P */ 24, 2, /* mux */ 0); static const char * const ahb2_parents[] = …; static const struct ccu_mux_fixed_prediv ahb2_fixed_predivs[] = …; static struct ccu_mux ahb2_clk = …; static SUNXI_CCU_GATE(bus_mipi_dsi_clk, "bus-mipi-dsi", "ahb1", 0x060, BIT(1), 0); static SUNXI_CCU_GATE(bus_ce_clk, "bus-ce", "ahb1", 0x060, BIT(5), 0); static SUNXI_CCU_GATE(bus_dma_clk, "bus-dma", "ahb1", 0x060, BIT(6), 0); static SUNXI_CCU_GATE(bus_mmc0_clk, "bus-mmc0", "ahb1", 0x060, BIT(8), 0); static SUNXI_CCU_GATE(bus_mmc1_clk, "bus-mmc1", "ahb1", 0x060, BIT(9), 0); static SUNXI_CCU_GATE(bus_mmc2_clk, "bus-mmc2", "ahb1", 0x060, BIT(10), 0); static SUNXI_CCU_GATE(bus_nand_clk, "bus-nand", "ahb1", 0x060, BIT(13), 0); static SUNXI_CCU_GATE(bus_dram_clk, "bus-dram", "ahb1", 0x060, BIT(14), 0); static SUNXI_CCU_GATE(bus_emac_clk, "bus-emac", "ahb2", 0x060, BIT(17), 0); static SUNXI_CCU_GATE(bus_ts_clk, "bus-ts", "ahb1", 0x060, BIT(18), 0); static SUNXI_CCU_GATE(bus_hstimer_clk, "bus-hstimer", "ahb1", 0x060, BIT(19), 0); static SUNXI_CCU_GATE(bus_spi0_clk, "bus-spi0", "ahb1", 0x060, BIT(20), 0); static SUNXI_CCU_GATE(bus_spi1_clk, "bus-spi1", "ahb1", 0x060, BIT(21), 0); static SUNXI_CCU_GATE(bus_otg_clk, "bus-otg", "ahb1", 0x060, BIT(23), 0); static SUNXI_CCU_GATE(bus_ehci0_clk, "bus-ehci0", "ahb1", 0x060, BIT(24), 0); static SUNXI_CCU_GATE(bus_ehci1_clk, "bus-ehci1", "ahb2", 0x060, BIT(25), 0); static SUNXI_CCU_GATE(bus_ohci0_clk, "bus-ohci0", "ahb1", 0x060, BIT(28), 0); static SUNXI_CCU_GATE(bus_ohci1_clk, "bus-ohci1", "ahb2", 0x060, BIT(29), 0); static SUNXI_CCU_GATE(bus_ve_clk, "bus-ve", "ahb1", 0x064, BIT(0), 0); static SUNXI_CCU_GATE(bus_tcon0_clk, "bus-tcon0", "ahb1", 0x064, BIT(3), 0); static SUNXI_CCU_GATE(bus_tcon1_clk, "bus-tcon1", "ahb1", 0x064, BIT(4), 0); static SUNXI_CCU_GATE(bus_deinterlace_clk, "bus-deinterlace", "ahb1", 0x064, BIT(5), 0); static SUNXI_CCU_GATE(bus_csi_clk, "bus-csi", "ahb1", 0x064, BIT(8), 0); static SUNXI_CCU_GATE(bus_hdmi_clk, "bus-hdmi", "ahb1", 0x064, BIT(11), 0); static SUNXI_CCU_GATE(bus_de_clk, "bus-de", "ahb1", 0x064, BIT(12), 0); static SUNXI_CCU_GATE(bus_gpu_clk, "bus-gpu", "ahb1", 0x064, BIT(20), 0); static SUNXI_CCU_GATE(bus_msgbox_clk, "bus-msgbox", "ahb1", 0x064, BIT(21), 0); static SUNXI_CCU_GATE(bus_spinlock_clk, "bus-spinlock", "ahb1", 0x064, BIT(22), 0); static SUNXI_CCU_GATE(bus_codec_clk, "bus-codec", "apb1", 0x068, BIT(0), 0); static SUNXI_CCU_GATE(bus_spdif_clk, "bus-spdif", "apb1", 0x068, BIT(1), 0); static SUNXI_CCU_GATE(bus_pio_clk, "bus-pio", "apb1", 0x068, BIT(5), 0); static SUNXI_CCU_GATE(bus_ths_clk, "bus-ths", "apb1", 0x068, BIT(8), 0); static SUNXI_CCU_GATE(bus_i2s0_clk, "bus-i2s0", "apb1", 0x068, BIT(12), 0); static SUNXI_CCU_GATE(bus_i2s1_clk, "bus-i2s1", "apb1", 0x068, BIT(13), 0); static SUNXI_CCU_GATE(bus_i2s2_clk, "bus-i2s2", "apb1", 0x068, BIT(14), 0); static SUNXI_CCU_GATE(bus_i2c0_clk, "bus-i2c0", "apb2", 0x06c, BIT(0), 0); static SUNXI_CCU_GATE(bus_i2c1_clk, "bus-i2c1", "apb2", 0x06c, BIT(1), 0); static SUNXI_CCU_GATE(bus_i2c2_clk, "bus-i2c2", "apb2", 0x06c, BIT(2), 0); static SUNXI_CCU_GATE(bus_scr_clk, "bus-scr", "apb2", 0x06c, BIT(5), 0); static SUNXI_CCU_GATE(bus_uart0_clk, "bus-uart0", "apb2", 0x06c, BIT(16), 0); static SUNXI_CCU_GATE(bus_uart1_clk, "bus-uart1", "apb2", 0x06c, BIT(17), 0); static SUNXI_CCU_GATE(bus_uart2_clk, "bus-uart2", "apb2", 0x06c, BIT(18), 0); static SUNXI_CCU_GATE(bus_uart3_clk, "bus-uart3", "apb2", 0x06c, BIT(19), 0); static SUNXI_CCU_GATE(bus_uart4_clk, "bus-uart4", "apb2", 0x06c, BIT(20), 0); static SUNXI_CCU_GATE(bus_dbg_clk, "bus-dbg", "ahb1", 0x070, BIT(7), 0); static struct clk_div_table ths_div_table[] = …; static const char * const ths_parents[] = …; static struct ccu_div ths_clk = …; static const char * const mod0_default_parents[] = …; static SUNXI_CCU_MP_WITH_MUX_GATE(nand_clk, "nand", mod0_default_parents, 0x080, 0, 4, /* M */ 16, 2, /* P */ 24, 2, /* mux */ BIT(31), /* gate */ 0); /* * MMC clocks are the new timing mode (see A83T & H3) variety, but without * the mode switch. This means they have a 2x post divider between the clock * and the MMC module. This is not documented in the manual, but is taken * into consideration when setting the mmc module clocks in the BSP kernel. * Without it, MMC performance is degraded. * * We model it here to be consistent with other SoCs supporting this mode. * The alternative would be to add the 2x multiplier when setting the MMC * module clock in the MMC driver, just for the A64. */ static const char * const mmc_default_parents[] = …; static SUNXI_CCU_MP_WITH_MUX_GATE_POSTDIV(mmc0_clk, "mmc0", mmc_default_parents, 0x088, 0, 4, /* M */ 16, 2, /* P */ 24, 2, /* mux */ BIT(31), /* gate */ 2, /* post-div */ 0); static SUNXI_CCU_MP_WITH_MUX_GATE_POSTDIV(mmc1_clk, "mmc1", mmc_default_parents, 0x08c, 0, 4, /* M */ 16, 2, /* P */ 24, 2, /* mux */ BIT(31), /* gate */ 2, /* post-div */ 0); static SUNXI_CCU_MP_WITH_MUX_GATE_POSTDIV(mmc2_clk, "mmc2", mmc_default_parents, 0x090, 0, 4, /* M */ 16, 2, /* P */ 24, 2, /* mux */ BIT(31), /* gate */ 2, /* post-div */ 0); static const char * const ts_parents[] = …; static SUNXI_CCU_MP_WITH_MUX_GATE(ts_clk, "ts", ts_parents, 0x098, 0, 4, /* M */ 16, 2, /* P */ 24, 4, /* mux */ BIT(31), /* gate */ 0); static SUNXI_CCU_MP_WITH_MUX_GATE(ce_clk, "ce", mmc_default_parents, 0x09c, 0, 4, /* M */ 16, 2, /* P */ 24, 2, /* mux */ BIT(31), /* gate */ 0); static SUNXI_CCU_MP_WITH_MUX_GATE(spi0_clk, "spi0", mod0_default_parents, 0x0a0, 0, 4, /* M */ 16, 2, /* P */ 24, 2, /* mux */ BIT(31), /* gate */ 0); static SUNXI_CCU_MP_WITH_MUX_GATE(spi1_clk, "spi1", mod0_default_parents, 0x0a4, 0, 4, /* M */ 16, 2, /* P */ 24, 2, /* mux */ BIT(31), /* gate */ 0); static const char * const i2s_parents[] = …; static SUNXI_CCU_MUX_WITH_GATE(i2s0_clk, "i2s0", i2s_parents, 0x0b0, 16, 2, BIT(31), CLK_SET_RATE_PARENT); static SUNXI_CCU_MUX_WITH_GATE(i2s1_clk, "i2s1", i2s_parents, 0x0b4, 16, 2, BIT(31), CLK_SET_RATE_PARENT); static SUNXI_CCU_MUX_WITH_GATE(i2s2_clk, "i2s2", i2s_parents, 0x0b8, 16, 2, BIT(31), CLK_SET_RATE_PARENT); static SUNXI_CCU_M_WITH_GATE(spdif_clk, "spdif", "pll-audio", 0x0c0, 0, 4, BIT(31), CLK_SET_RATE_PARENT); static SUNXI_CCU_GATE(usb_phy0_clk, "usb-phy0", "osc24M", 0x0cc, BIT(8), 0); static SUNXI_CCU_GATE(usb_phy1_clk, "usb-phy1", "osc24M", 0x0cc, BIT(9), 0); static SUNXI_CCU_GATE(usb_hsic_clk, "usb-hsic", "pll-hsic", 0x0cc, BIT(10), 0); static SUNXI_CCU_GATE(usb_hsic_12m_clk, "usb-hsic-12M", "osc12M", 0x0cc, BIT(11), 0); static SUNXI_CCU_GATE(usb_ohci0_clk, "usb-ohci0", "osc12M", 0x0cc, BIT(16), 0); static SUNXI_CCU_GATE(usb_ohci1_clk, "usb-ohci1", "usb-ohci0", 0x0cc, BIT(17), 0); static const char * const dram_parents[] = …; static SUNXI_CCU_M_WITH_MUX(dram_clk, "dram", dram_parents, 0x0f4, 0, 4, 20, 2, CLK_IS_CRITICAL); static SUNXI_CCU_GATE(dram_ve_clk, "dram-ve", "dram", 0x100, BIT(0), 0); static SUNXI_CCU_GATE(dram_csi_clk, "dram-csi", "dram", 0x100, BIT(1), 0); static SUNXI_CCU_GATE(dram_deinterlace_clk, "dram-deinterlace", "dram", 0x100, BIT(2), 0); static SUNXI_CCU_GATE(dram_ts_clk, "dram-ts", "dram", 0x100, BIT(3), 0); static const char * const de_parents[] = …; static SUNXI_CCU_M_WITH_MUX_GATE(de_clk, "de", de_parents, 0x104, 0, 4, 24, 3, BIT(31), CLK_SET_RATE_PARENT); /* * DSI output seems to work only when PLL_MIPI selected. Set it and prevent * the mux from reparenting. */ #define SUN50I_A64_TCON0_CLK_REG … static const char * const tcon0_parents[] = …; static const u8 tcon0_table[] = …; static SUNXI_CCU_MUX_TABLE_WITH_GATE_CLOSEST(tcon0_clk, "tcon0", tcon0_parents, tcon0_table, 0x118, 24, 3, BIT(31), CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT); static const char * const tcon1_parents[] = …; static const u8 tcon1_table[] = …; static SUNXI_CCU_M_WITH_MUX_TABLE_GATE_CLOSEST(tcon1_clk, "tcon1", tcon1_parents, tcon1_table, 0x11c, 0, 4, /* M */ 24, 2, /* mux */ BIT(31), /* gate */ CLK_SET_RATE_PARENT); static const char * const deinterlace_parents[] = …; static SUNXI_CCU_M_WITH_MUX_GATE(deinterlace_clk, "deinterlace", deinterlace_parents, 0x124, 0, 4, 24, 3, BIT(31), 0); static SUNXI_CCU_GATE(csi_misc_clk, "csi-misc", "osc24M", 0x130, BIT(31), 0); static const char * const csi_sclk_parents[] = …; static SUNXI_CCU_M_WITH_MUX_GATE(csi_sclk_clk, "csi-sclk", csi_sclk_parents, 0x134, 16, 4, 24, 3, BIT(31), 0); static const char * const csi_mclk_parents[] = …; static SUNXI_CCU_M_WITH_MUX_GATE(csi_mclk_clk, "csi-mclk", csi_mclk_parents, 0x134, 0, 5, 8, 3, BIT(15), 0); static SUNXI_CCU_M_WITH_GATE(ve_clk, "ve", "pll-ve", 0x13c, 16, 3, BIT(31), CLK_SET_RATE_PARENT); static SUNXI_CCU_GATE(ac_dig_clk, "ac-dig", "pll-audio", 0x140, BIT(31), CLK_SET_RATE_PARENT); static SUNXI_CCU_GATE(ac_dig_4x_clk, "ac-dig-4x", "pll-audio-4x", 0x140, BIT(30), CLK_SET_RATE_PARENT); static SUNXI_CCU_GATE(avs_clk, "avs", "osc24M", 0x144, BIT(31), 0); static const char * const hdmi_parents[] = …; static SUNXI_CCU_M_WITH_MUX_GATE_CLOSEST(hdmi_clk, "hdmi", hdmi_parents, 0x150, 0, 4, 24, 2, BIT(31), CLK_SET_RATE_PARENT); static SUNXI_CCU_GATE(hdmi_ddc_clk, "hdmi-ddc", "osc24M", 0x154, BIT(31), 0); static const char * const mbus_parents[] = …; static SUNXI_CCU_M_WITH_MUX_GATE(mbus_clk, "mbus", mbus_parents, 0x15c, 0, 3, 24, 2, BIT(31), CLK_IS_CRITICAL); static const char * const dsi_dphy_parents[] = …; static const u8 dsi_dphy_table[] = …; static SUNXI_CCU_M_WITH_MUX_TABLE_GATE_CLOSEST(dsi_dphy_clk, "dsi-dphy", dsi_dphy_parents, dsi_dphy_table, 0x168, 0, 4, 8, 2, BIT(15), CLK_SET_RATE_PARENT); static SUNXI_CCU_M_WITH_GATE(gpu_clk, "gpu", "pll-gpu", 0x1a0, 0, 3, BIT(31), CLK_SET_RATE_PARENT); /* Fixed Factor clocks */ static CLK_FIXED_FACTOR_FW_NAME(osc12M_clk, "osc12M", "hosc", 2, 1, 0); static const struct clk_hw *clk_parent_pll_audio[] = …; /* We hardcode the divider to 1 for now */ static CLK_FIXED_FACTOR_HWS(pll_audio_clk, "pll-audio", clk_parent_pll_audio, 1, 1, CLK_SET_RATE_PARENT); static CLK_FIXED_FACTOR_HWS(pll_audio_2x_clk, "pll-audio-2x", clk_parent_pll_audio, 2, 1, CLK_SET_RATE_PARENT); static CLK_FIXED_FACTOR_HWS(pll_audio_4x_clk, "pll-audio-4x", clk_parent_pll_audio, 1, 1, CLK_SET_RATE_PARENT); static CLK_FIXED_FACTOR_HWS(pll_audio_8x_clk, "pll-audio-8x", clk_parent_pll_audio, 1, 2, CLK_SET_RATE_PARENT); static CLK_FIXED_FACTOR_HW(pll_periph0_2x_clk, "pll-periph0-2x", &pll_periph0_clk.common.hw, 1, 2, 0); static CLK_FIXED_FACTOR_HW(pll_periph1_2x_clk, "pll-periph1-2x", &pll_periph1_clk.common.hw, 1, 2, 0); static CLK_FIXED_FACTOR_HW(pll_video0_2x_clk, "pll-video0-2x", &pll_video0_clk.common.hw, 1, 2, CLK_SET_RATE_PARENT); static struct ccu_common *sun50i_a64_ccu_clks[] = …; static struct clk_hw_onecell_data sun50i_a64_hw_clks = …; static struct ccu_reset_map sun50i_a64_ccu_resets[] = …; static const struct sunxi_ccu_desc sun50i_a64_ccu_desc = …; static struct ccu_pll_nb sun50i_a64_pll_cpu_nb = …; static struct ccu_mux_nb sun50i_a64_cpu_nb = …; static int sun50i_a64_ccu_probe(struct platform_device *pdev) { … } static const struct of_device_id sun50i_a64_ccu_ids[] = …; MODULE_DEVICE_TABLE(of, sun50i_a64_ccu_ids); static struct platform_driver sun50i_a64_ccu_driver = …; module_platform_driver(…) …; MODULE_IMPORT_NS(…); MODULE_DESCRIPTION(…) …; MODULE_LICENSE(…) …;
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