/* SPDX-License-Identifier: GPL-2.0 */ /* * Copyright (c) 2020 Yangtao Li <[email protected]> */ #ifndef _CCU_SUN50I_A100_H_ #define _CCU_SUN50I_A100_H_ #include <dt-bindings/clock/sun50i-a100-ccu.h> #include <dt-bindings/reset/sun50i-a100-ccu.h> #define CLK_OSC12M … #define CLK_PLL_CPUX … #define CLK_PLL_DDR0 … /* PLL_PERIPH0 exported for PRCM */ #define CLK_PLL_PERIPH0_2X … #define CLK_PLL_PERIPH1 … #define CLK_PLL_PERIPH1_2X … #define CLK_PLL_GPU … #define CLK_PLL_VIDEO0 … #define CLK_PLL_VIDEO0_2X … #define CLK_PLL_VIDEO0_4X … #define CLK_PLL_VIDEO1 … #define CLK_PLL_VIDEO1_2X … #define CLK_PLL_VIDEO1_4X … #define CLK_PLL_VIDEO2 … #define CLK_PLL_VIDEO2_2X … #define CLK_PLL_VIDEO2_4X … #define CLK_PLL_VIDEO3 … #define CLK_PLL_VIDEO3_2X … #define CLK_PLL_VIDEO3_4X … #define CLK_PLL_VE … #define CLK_PLL_COM … #define CLK_PLL_COM_AUDIO … #define CLK_PLL_AUDIO … /* CPUX clock exported for DVFS */ #define CLK_AXI … #define CLK_CPUX_APB … #define CLK_PSI_AHB1_AHB2 … #define CLK_AHB3 … /* APB1 clock exported for PIO */ #define CLK_APB2 … /* All module clocks and bus gates are exported except DRAM */ #define CLK_BUS_DRAM … #define CLK_NUMBER … #endif /* _CCU_SUN50I_A100_H_ */
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