// SPDX-License-Identifier: GPL-2.0 /* * Copyright (c) 2020 Yangtao Li <[email protected]> */ #include <linux/clk-provider.h> #include <linux/io.h> #include <linux/module.h> #include <linux/platform_device.h> #include "ccu_common.h" #include "ccu_reset.h" #include "ccu_div.h" #include "ccu_gate.h" #include "ccu_mp.h" #include "ccu_mult.h" #include "ccu_nk.h" #include "ccu_nkm.h" #include "ccu_nkmp.h" #include "ccu_nm.h" #include "ccu-sun50i-a100.h" #define SUN50I_A100_PLL_SDM_ENABLE … #define SUN50I_A100_PLL_OUTPUT_ENABLE … #define SUN50I_A100_PLL_LOCK … #define SUN50I_A100_PLL_LOCK_ENABLE … #define SUN50I_A100_PLL_ENABLE … #define SUN50I_A100_PLL_PERIPH1_PATTERN0 … /* * The CPU PLL is actually NP clock, with P being /1, /2 or /4. However * P should only be used for output frequencies lower than 288 MHz. * * For now we can just model it as a multiplier clock, and force P to /1. * * The M factor is present in the register's description, but not in the * frequency formula, and it's documented as "M is only used for backdoor * testing", so it's not modelled and then force to 0. */ #define SUN50I_A100_PLL_CPUX_REG … static struct ccu_mult pll_cpux_clk = …; /* Some PLLs are input * N / div1 / P. Model them as NKMP with no K */ #define SUN50I_A100_PLL_DDR0_REG … static struct ccu_nkmp pll_ddr0_clk = …; #define SUN50I_A100_PLL_PERIPH0_REG … static struct ccu_nkmp pll_periph0_clk = …; #define SUN50I_A100_PLL_PERIPH1_REG … static struct ccu_nkmp pll_periph1_clk = …; #define SUN50I_A100_PLL_PERIPH1_PATTERN0_REG … #define SUN50I_A100_PLL_GPU_REG … static struct ccu_nkmp pll_gpu_clk = …; /* * For Video PLLs, the output divider is described as "used for testing" * in the user manual. So it's not modelled and forced to 0. */ #define SUN50I_A100_PLL_VIDEO0_REG … static struct ccu_nm pll_video0_clk = …; #define SUN50I_A100_PLL_VIDEO1_REG … static struct ccu_nm pll_video1_clk = …; #define SUN50I_A100_PLL_VIDEO2_REG … static struct ccu_nm pll_video2_clk = …; #define SUN50I_A100_PLL_VE_REG … static struct ccu_nkmp pll_ve_clk = …; /* * The COM PLL has m0 dividers in addition to the usual N, M * factors. Since we only need 1 frequencies from this PLL: 45.1584 MHz, * ignore it for now. */ #define SUN50I_A100_PLL_COM_REG … static struct ccu_sdm_setting pll_com_sdm_table[] = …; static struct ccu_nm pll_com_clk = …; #define SUN50I_A100_PLL_VIDEO3_REG … static struct ccu_nm pll_video3_clk = …; /* * The Audio PLL has m0, m1 dividers in addition to the usual N, M * factors. Since we only need 4 frequencies from this PLL: 22.5792 MHz, * 24.576 MHz, 90.3168MHz and 98.304MHz ignore them for now. * Enforce the default for them, which is m0 = 1, m1 = 0. */ #define SUN50I_A100_PLL_AUDIO_REG … static struct ccu_sdm_setting pll_audio_sdm_table[] = …; static struct ccu_nm pll_audio_clk = …; static const char * const cpux_parents[] = …; static SUNXI_CCU_MUX(cpux_clk, "cpux", cpux_parents, 0x500, 24, 3, CLK_SET_RATE_PARENT | CLK_IS_CRITICAL); static SUNXI_CCU_M(axi_clk, "axi", "cpux", 0x500, 0, 2, 0); static SUNXI_CCU_M(cpux_apb_clk, "cpux-apb", "cpux", 0x500, 8, 2, 0); static const char * const psi_ahb1_ahb2_parents[] = …; static SUNXI_CCU_MP_WITH_MUX(psi_ahb1_ahb2_clk, "psi-ahb1-ahb2", psi_ahb1_ahb2_parents, 0x510, 0, 2, /* M */ 8, 2, /* P */ 24, 3, /* mux */ 0); static const char * const ahb3_apb1_apb2_parents[] = …; static SUNXI_CCU_MP_WITH_MUX(ahb3_clk, "ahb3", ahb3_apb1_apb2_parents, 0x51c, 0, 2, /* M */ 8, 2, /* P */ 24, 3, /* mux */ 0); static SUNXI_CCU_MP_WITH_MUX(apb1_clk, "apb1", ahb3_apb1_apb2_parents, 0x520, 0, 2, /* M */ 8, 2, /* P */ 24, 3, /* mux */ 0); static SUNXI_CCU_MP_WITH_MUX(apb2_clk, "apb2", ahb3_apb1_apb2_parents, 0x524, 0, 2, /* M */ 8, 2, /* P */ 24, 3, /* mux */ 0); static const char * const mbus_parents[] = …; static SUNXI_CCU_M_WITH_MUX_GATE(mbus_clk, "mbus", mbus_parents, 0x540, 0, 3, /* M */ 24, 2, /* mux */ BIT(31), /* gate */ CLK_IS_CRITICAL); static const char * const de_parents[] = …; static SUNXI_CCU_M_WITH_MUX_GATE(de_clk, "de0", de_parents, 0x600, 0, 4, /* M */ 24, 1, /* mux */ BIT(31), /* gate */ CLK_SET_RATE_PARENT); static SUNXI_CCU_GATE(bus_de_clk, "bus-de", "psi-ahb1-ahb2", 0x60c, BIT(0), 0); static const char * const g2d_parents[] = …; static SUNXI_CCU_M_WITH_MUX_GATE(g2d_clk, "g2d", g2d_parents, 0x630, 0, 4, /* M */ 24, 3, /* mux */ BIT(31), /* gate */ 0); static SUNXI_CCU_GATE(bus_g2d_clk, "bus-g2d", "psi-ahb1-ahb2", 0x63c, BIT(0), 0); static const char * const gpu_parents[] = …; static SUNXI_CCU_M_WITH_MUX_GATE(gpu_clk, "gpu", gpu_parents, 0x670, 0, 2, /* M */ 24, 1, /* mux */ BIT(31), /* gate */ 0); static SUNXI_CCU_GATE(bus_gpu_clk, "bus-gpu", "psi-ahb1-ahb2", 0x67c, BIT(0), 0); static const char * const ce_parents[] = …; static SUNXI_CCU_MP_WITH_MUX_GATE(ce_clk, "ce", ce_parents, 0x680, 0, 4, /* M */ 8, 2, /* P */ 24, 1, /* mux */ BIT(31), /* gate */ 0); static SUNXI_CCU_GATE(bus_ce_clk, "bus-ce", "psi-ahb1-ahb2", 0x68c, BIT(0), 0); static const char * const ve_parents[] = …; static SUNXI_CCU_M_WITH_MUX_GATE(ve_clk, "ve", ve_parents, 0x690, 0, 3, /* M */ 24, 1, /* mux */ BIT(31), /* gate */ CLK_SET_RATE_PARENT); static SUNXI_CCU_GATE(bus_ve_clk, "bus-ve", "psi-ahb1-ahb2", 0x69c, BIT(0), 0); static SUNXI_CCU_GATE(bus_dma_clk, "bus-dma", "psi-ahb1-ahb2", 0x70c, BIT(0), 0); static SUNXI_CCU_GATE(bus_msgbox_clk, "bus-msgbox", "psi-ahb1-ahb2", 0x71c, BIT(0), 0); static SUNXI_CCU_GATE(bus_spinlock_clk, "bus-spinlock", "psi-ahb1-ahb2", 0x72c, BIT(0), 0); static SUNXI_CCU_GATE(bus_hstimer_clk, "bus-hstimer", "psi-ahb1-ahb2", 0x73c, BIT(0), 0); static SUNXI_CCU_GATE(avs_clk, "avs", "dcxo24M", 0x740, BIT(31), 0); static SUNXI_CCU_GATE(bus_dbg_clk, "bus-dbg", "psi-ahb1-ahb2", 0x78c, BIT(0), 0); static SUNXI_CCU_GATE(bus_psi_clk, "bus-psi", "psi-ahb1-ahb2", 0x79c, BIT(0), 0); static SUNXI_CCU_GATE(bus_pwm_clk, "bus-pwm", "apb1", 0x7ac, BIT(0), 0); static SUNXI_CCU_GATE(bus_iommu_clk, "bus-iommu", "apb1", 0x7bc, BIT(0), 0); static SUNXI_CCU_GATE(mbus_dma_clk, "mbus-dma", "mbus", 0x804, BIT(0), 0); static SUNXI_CCU_GATE(mbus_ve_clk, "mbus-ve", "mbus", 0x804, BIT(1), 0); static SUNXI_CCU_GATE(mbus_ce_clk, "mbus-ce", "mbus", 0x804, BIT(2), 0); static SUNXI_CCU_GATE(mbus_nand_clk, "mbus-nand", "mbus", 0x804, BIT(5), 0); static SUNXI_CCU_GATE(mbus_csi_clk, "mbus-csi", "mbus", 0x804, BIT(8), 0); static SUNXI_CCU_GATE(mbus_isp_clk, "mbus-isp", "mbus", 0x804, BIT(9), 0); static SUNXI_CCU_GATE(mbus_g2d_clk, "mbus-g2d", "mbus", 0x804, BIT(10), 0); static SUNXI_CCU_GATE(bus_dram_clk, "bus-dram", "psi-ahb1-ahb2", 0x80c, BIT(0), CLK_IS_CRITICAL); static const char * const nand_spi_parents[] = …; static SUNXI_CCU_MP_WITH_MUX_GATE(nand0_clk, "nand0", nand_spi_parents, 0x810, 0, 4, /* M */ 8, 2, /* P */ 24, 3, /* mux */ BIT(31), /* gate */ 0); static SUNXI_CCU_MP_WITH_MUX_GATE(nand1_clk, "nand1", nand_spi_parents, 0x814, 0, 4, /* M */ 8, 2, /* P */ 24, 3, /* mux */ BIT(31), /* gate */ 0); static SUNXI_CCU_GATE(bus_nand_clk, "bus-nand", "ahb3", 0x82c, BIT(0), 0); static const char * const mmc_parents[] = …; static SUNXI_CCU_MP_WITH_MUX_GATE_POSTDIV(mmc0_clk, "mmc0", mmc_parents, 0x830, 0, 4, /* M */ 8, 2, /* P */ 24, 2, /* mux */ BIT(31), /* gate */ 2, /* post-div */ CLK_SET_RATE_NO_REPARENT); static SUNXI_CCU_MP_WITH_MUX_GATE_POSTDIV(mmc1_clk, "mmc1", mmc_parents, 0x834, 0, 4, /* M */ 8, 2, /* P */ 24, 2, /* mux */ BIT(31), /* gate */ 2, /* post-div */ CLK_SET_RATE_NO_REPARENT); static SUNXI_CCU_MP_WITH_MUX_GATE_POSTDIV(mmc2_clk, "mmc2", mmc_parents, 0x838, 0, 4, /* M */ 8, 2, /* P */ 24, 2, /* mux */ BIT(31), /* gate */ 2, /* post-div */ CLK_SET_RATE_NO_REPARENT); static SUNXI_CCU_GATE(bus_mmc0_clk, "bus-mmc0", "ahb3", 0x84c, BIT(0), 0); static SUNXI_CCU_GATE(bus_mmc1_clk, "bus-mmc1", "ahb3", 0x84c, BIT(1), 0); static SUNXI_CCU_GATE(bus_mmc2_clk, "bus-mmc2", "ahb3", 0x84c, BIT(2), 0); static SUNXI_CCU_GATE(bus_uart0_clk, "bus-uart0", "apb2", 0x90c, BIT(0), 0); static SUNXI_CCU_GATE(bus_uart1_clk, "bus-uart1", "apb2", 0x90c, BIT(1), 0); static SUNXI_CCU_GATE(bus_uart2_clk, "bus-uart2", "apb2", 0x90c, BIT(2), 0); static SUNXI_CCU_GATE(bus_uart3_clk, "bus-uart3", "apb2", 0x90c, BIT(3), 0); static SUNXI_CCU_GATE(bus_uart4_clk, "bus-uart4", "apb2", 0x90c, BIT(4), 0); static SUNXI_CCU_GATE(bus_i2c0_clk, "bus-i2c0", "apb2", 0x91c, BIT(0), 0); static SUNXI_CCU_GATE(bus_i2c1_clk, "bus-i2c1", "apb2", 0x91c, BIT(1), 0); static SUNXI_CCU_GATE(bus_i2c2_clk, "bus-i2c2", "apb2", 0x91c, BIT(2), 0); static SUNXI_CCU_GATE(bus_i2c3_clk, "bus-i2c3", "apb2", 0x91c, BIT(3), 0); static SUNXI_CCU_MP_WITH_MUX_GATE(spi0_clk, "spi0", nand_spi_parents, 0x940, 0, 4, /* M */ 8, 2, /* P */ 24, 3, /* mux */ BIT(31), /* gate */ 0); static SUNXI_CCU_MP_WITH_MUX_GATE(spi1_clk, "spi1", nand_spi_parents, 0x944, 0, 4, /* M */ 8, 2, /* P */ 24, 3, /* mux */ BIT(31), /* gate */ 0); static SUNXI_CCU_MP_WITH_MUX_GATE(spi2_clk, "spi2", nand_spi_parents, 0x948, 0, 4, /* M */ 8, 2, /* P */ 24, 3, /* mux */ BIT(31), /* gate */ 0); static SUNXI_CCU_GATE(bus_spi0_clk, "bus-spi0", "ahb3", 0x96c, BIT(0), 0); static SUNXI_CCU_GATE(bus_spi1_clk, "bus-spi1", "ahb3", 0x96c, BIT(1), 0); static SUNXI_CCU_GATE(bus_spi2_clk, "bus-spi2", "ahb3", 0x96c, BIT(2), 0); static SUNXI_CCU_GATE(emac_25m_clk, "emac-25m", "ahb3", 0x970, BIT(31) | BIT(30), 0); static SUNXI_CCU_GATE(bus_emac_clk, "bus-emac", "ahb3", 0x97c, BIT(0), 0); static const char * const ir_parents[] = …; static SUNXI_CCU_MP_WITH_MUX_GATE(ir_rx_clk, "ir-rx", ir_parents, 0x990, 0, 4, /* M */ 8, 2, /* P */ 24, 3, /* mux */ BIT(31), /* gate */ 0); static SUNXI_CCU_GATE(bus_ir_rx_clk, "bus-ir-rx", "ahb3", 0x99c, BIT(0), 0); static SUNXI_CCU_MP_WITH_MUX_GATE(ir_tx_clk, "ir-tx", ir_parents, 0x9c0, 0, 4, /* M */ 8, 2, /* P */ 24, 3, /* mux */ BIT(31), /* gate */ 0); static SUNXI_CCU_GATE(bus_ir_tx_clk, "bus-ir-tx", "apb1", 0x9cc, BIT(0), 0); static SUNXI_CCU_GATE(bus_gpadc_clk, "bus-gpadc", "apb1", 0x9ec, BIT(0), 0); static SUNXI_CCU_GATE(bus_ths_clk, "bus-ths", "apb1", 0x9fc, BIT(0), 0); static const char * const audio_parents[] = …; static struct ccu_div i2s0_clk = …; static struct ccu_div i2s1_clk = …; static struct ccu_div i2s2_clk = …; static struct ccu_div i2s3_clk = …; static SUNXI_CCU_GATE(bus_i2s0_clk, "bus-i2s0", "apb1", 0xa20, BIT(0), 0); static SUNXI_CCU_GATE(bus_i2s1_clk, "bus-i2s1", "apb1", 0xa20, BIT(1), 0); static SUNXI_CCU_GATE(bus_i2s2_clk, "bus-i2s2", "apb1", 0xa20, BIT(2), 0); static SUNXI_CCU_GATE(bus_i2s3_clk, "bus-i2s3", "apb1", 0xa20, BIT(3), 0); static struct ccu_div spdif_clk = …; static SUNXI_CCU_GATE(bus_spdif_clk, "bus-spdif", "apb1", 0xa2c, BIT(0), 0); static struct ccu_div dmic_clk = …; static SUNXI_CCU_GATE(bus_dmic_clk, "bus-dmic", "apb1", 0xa4c, BIT(0), 0); static SUNXI_CCU_M_WITH_MUX_GATE(audio_codec_dac_clk, "audio-codec-dac", audio_parents, 0xa50, 0, 4, /* M */ 24, 2, /* mux */ BIT(31), /* gate */ 0); static SUNXI_CCU_M_WITH_MUX_GATE(audio_codec_adc_clk, "audio-codec-adc", audio_parents, 0xa54, 0, 4, /* M */ 24, 2, /* mux */ BIT(31), /* gate */ 0); static SUNXI_CCU_M_WITH_MUX_GATE(audio_codec_4x_clk, "audio-codec-4x", audio_parents, 0xa58, 0, 4, /* M */ 24, 2, /* mux */ BIT(31), /* gate */ 0); static SUNXI_CCU_GATE(bus_audio_codec_clk, "bus-audio-codec", "apb1", 0xa5c, BIT(0), 0); /* * There are OHCI 12M clock source selection bits for 2 USB 2.0 ports. * We will force them to 0 (12M divided from 48M). */ #define SUN50I_A100_USB0_CLK_REG … #define SUN50I_A100_USB1_CLK_REG … static SUNXI_CCU_GATE(usb_ohci0_clk, "usb-ohci0", "osc12M", 0xa70, BIT(31), 0); static SUNXI_CCU_GATE(usb_phy0_clk, "usb-phy0", "dcxo24M", 0xa70, BIT(29), 0); static SUNXI_CCU_GATE(usb_ohci1_clk, "usb-ohci1", "osc12M", 0xa74, BIT(31), 0); static SUNXI_CCU_GATE(usb_phy1_clk, "usb-phy1", "dcxo24M", 0xa74, BIT(29), 0); static SUNXI_CCU_GATE(bus_ohci0_clk, "bus-ohci0", "ahb3", 0xa8c, BIT(0), 0); static SUNXI_CCU_GATE(bus_ohci1_clk, "bus-ohci1", "ahb3", 0xa8c, BIT(1), 0); static SUNXI_CCU_GATE(bus_ehci0_clk, "bus-ehci0", "ahb3", 0xa8c, BIT(4), 0); static SUNXI_CCU_GATE(bus_ehci1_clk, "bus-ehci1", "ahb3", 0xa8c, BIT(5), 0); static SUNXI_CCU_GATE(bus_otg_clk, "bus-otg", "ahb3", 0xa8c, BIT(8), 0); static SUNXI_CCU_GATE(bus_lradc_clk, "bus-lradc", "ahb3", 0xa9c, BIT(0), 0); static SUNXI_CCU_GATE(bus_dpss_top0_clk, "bus-dpss-top0", "ahb3", 0xabc, BIT(0), 0); static SUNXI_CCU_GATE(bus_dpss_top1_clk, "bus-dpss-top1", "ahb3", 0xacc, BIT(0), 0); static const char * const mipi_dsi_parents[] = …; static SUNXI_CCU_M_WITH_MUX_GATE(mipi_dsi_clk, "mipi-dsi", mipi_dsi_parents, 0xb24, 0, 4, /* M */ 24, 2, /* mux */ BIT(31), /* gate */ 0); static SUNXI_CCU_GATE(bus_mipi_dsi_clk, "bus-mipi-dsi", "ahb3", 0xb4c, BIT(0), 0); static const char * const tcon_lcd_parents[] = …; static SUNXI_CCU_MP_WITH_MUX_GATE(tcon_lcd_clk, "tcon-lcd0", tcon_lcd_parents, 0xb60, 0, 4, /* M */ 8, 2, /* P */ 24, 3, /* mux */ BIT(31), /* gate */ 0); static SUNXI_CCU_GATE(bus_tcon_lcd_clk, "bus-tcon-lcd0", "ahb3", 0xb7c, BIT(0), 0); static const char * const ledc_parents[] = …; static SUNXI_CCU_MP_WITH_MUX_GATE(ledc_clk, "ledc", ledc_parents, 0xbf0, 0, 4, /* M */ 8, 2, /* P */ 24, 3, /* mux */ BIT(31), /* gate */ 0); static SUNXI_CCU_GATE(bus_ledc_clk, "bus-ledc", "ahb3", 0xbfc, BIT(0), 0); static const char * const csi_top_parents[] = …; static SUNXI_CCU_M_WITH_MUX_GATE(csi_top_clk, "csi-top", csi_top_parents, 0xc04, 0, 4, /* M */ 24, 3, /* mux */ BIT(31), /* gate */ 0); static const char * const csi0_mclk_parents[] = …; static SUNXI_CCU_M_WITH_MUX_GATE(csi0_mclk_clk, "csi0-mclk", csi0_mclk_parents, 0xc08, 0, 5, /* M */ 24, 3, /* mux */ BIT(31), /* gate */ 0); static const char * const csi1_mclk_parents[] = …; static SUNXI_CCU_M_WITH_MUX_GATE(csi1_mclk_clk, "csi1-mclk", csi1_mclk_parents, 0xc0c, 0, 5, /* M */ 24, 3, /* mux */ BIT(31), /* gate */ 0); static SUNXI_CCU_GATE(bus_csi_clk, "bus-csi", "ahb3", 0xc1c, BIT(0), 0); static const char * const csi_isp_parents[] = …; static SUNXI_CCU_M_WITH_MUX_GATE(csi_isp_clk, "csi-isp", csi_isp_parents, 0xc20, 0, 5, /* M */ 24, 3, /* mux */ BIT(31), /* gate */ 0); /* Fixed factor clocks */ static CLK_FIXED_FACTOR_FW_NAME(osc12M_clk, "osc12M", "hosc", 2, 1, 0); static CLK_FIXED_FACTOR_HW(pll_com_audio_clk, "pll-com-audio", &pll_com_clk.common.hw, 5, 1, CLK_SET_RATE_PARENT); static CLK_FIXED_FACTOR_HW(pll_periph0_2x_clk, "pll-periph0-2x", &pll_periph0_clk.common.hw, 1, 2, 0); static CLK_FIXED_FACTOR_HW(pll_periph1_2x_clk, "pll-periph1-2x", &pll_periph1_clk.common.hw, 1, 2, 0); static const struct clk_hw *pll_video0_parents[] = …; static CLK_FIXED_FACTOR_HWS(pll_video0_4x_clk, "pll-video0-4x", pll_video0_parents, 1, 4, CLK_SET_RATE_PARENT); static CLK_FIXED_FACTOR_HWS(pll_video0_2x_clk, "pll-video0-2x", pll_video0_parents, 1, 2, CLK_SET_RATE_PARENT); static const struct clk_hw *pll_video1_parents[] = …; static CLK_FIXED_FACTOR_HWS(pll_video1_4x_clk, "pll-video1-4x", pll_video1_parents, 1, 4, CLK_SET_RATE_PARENT); static CLK_FIXED_FACTOR_HWS(pll_video1_2x_clk, "pll-video1-2x", pll_video1_parents, 1, 2, CLK_SET_RATE_PARENT); static const struct clk_hw *pll_video2_parents[] = …; static CLK_FIXED_FACTOR_HWS(pll_video2_4x_clk, "pll-video2-4x", pll_video2_parents, 1, 4, CLK_SET_RATE_PARENT); static CLK_FIXED_FACTOR_HWS(pll_video2_2x_clk, "pll-video2-2x", pll_video2_parents, 1, 2, CLK_SET_RATE_PARENT); static const struct clk_hw *pll_video3_parents[] = …; static CLK_FIXED_FACTOR_HWS(pll_video3_4x_clk, "pll-video3-4x", pll_video3_parents, 1, 4, CLK_SET_RATE_PARENT); static CLK_FIXED_FACTOR_HWS(pll_video3_2x_clk, "pll-video3-2x", pll_video3_parents, 1, 2, CLK_SET_RATE_PARENT); static struct ccu_common *sun50i_a100_ccu_clks[] = …; static struct clk_hw_onecell_data sun50i_a100_hw_clks = …; static struct ccu_reset_map sun50i_a100_ccu_resets[] = …; static const struct sunxi_ccu_desc sun50i_a100_ccu_desc = …; static const u32 sun50i_a100_pll_regs[] = …; static const u32 sun50i_a100_pll_video_regs[] = …; static const u32 sun50i_a100_usb2_clk_regs[] = …; static struct ccu_pll_nb sun50i_a100_pll_cpu_nb = …; static struct ccu_mux_nb sun50i_a100_cpu_nb = …; static int sun50i_a100_ccu_probe(struct platform_device *pdev) { … } static const struct of_device_id sun50i_a100_ccu_ids[] = …; MODULE_DEVICE_TABLE(of, sun50i_a100_ccu_ids); static struct platform_driver sun50i_a100_ccu_driver = …; module_platform_driver(…) …; MODULE_IMPORT_NS(…); MODULE_DESCRIPTION(…) …; MODULE_LICENSE(…) …;
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