// SPDX-License-Identifier: GPL-2.0 /* * Copyright (c) 2016 Icenowy Zheng <[email protected]> * */ #include <linux/clk-provider.h> #include <linux/io.h> #include <linux/module.h> #include <linux/platform_device.h> #include "ccu_common.h" #include "ccu_reset.h" #include "ccu_div.h" #include "ccu_gate.h" #include "ccu_mp.h" #include "ccu_mult.h" #include "ccu_nk.h" #include "ccu_nkm.h" #include "ccu_nkmp.h" #include "ccu_nm.h" #include "ccu_phase.h" #include "ccu-suniv-f1c100s.h" static struct ccu_nkmp pll_cpu_clk = …; /* * The Audio PLL is supposed to have 4 outputs: 3 fixed factors from * the base (2x, 4x and 8x), and one variable divider (the one true * pll audio). * * We don't have any need for the variable divider for now, so we just * hardcode it to match with the clock names */ #define SUNIV_PLL_AUDIO_REG … static SUNXI_CCU_NM_WITH_GATE_LOCK(pll_audio_base_clk, "pll-audio-base", "osc24M", 0x008, 8, 7, /* N */ 0, 5, /* M */ BIT(31), /* gate */ BIT(28), /* lock */ CLK_SET_RATE_UNGATE); static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_video_clk, "pll-video", "osc24M", 0x010, 8, 7, /* N */ 0, 4, /* M */ BIT(24), /* frac enable */ BIT(25), /* frac select */ 270000000, /* frac rate 0 */ 297000000, /* frac rate 1 */ BIT(31), /* gate */ BIT(28), /* lock */ CLK_SET_RATE_UNGATE); static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_ve_clk, "pll-ve", "osc24M", 0x018, 8, 7, /* N */ 0, 4, /* M */ BIT(24), /* frac enable */ BIT(25), /* frac select */ 270000000, /* frac rate 0 */ 297000000, /* frac rate 1 */ BIT(31), /* gate */ BIT(28), /* lock */ CLK_SET_RATE_UNGATE); static SUNXI_CCU_NKM_WITH_GATE_LOCK(pll_ddr0_clk, "pll-ddr", "osc24M", 0x020, 8, 5, /* N */ 4, 2, /* K */ 0, 2, /* M */ BIT(31), /* gate */ BIT(28), /* lock */ CLK_IS_CRITICAL); static struct ccu_nk pll_periph_clk = …; static const char * const cpu_parents[] = …; static SUNXI_CCU_MUX(cpu_clk, "cpu", cpu_parents, 0x050, 16, 2, CLK_IS_CRITICAL | CLK_SET_RATE_PARENT); static const char * const ahb_parents[] = …; static const struct ccu_mux_var_prediv ahb_predivs[] = …; static struct ccu_div ahb_clk = …; static struct clk_div_table apb_div_table[] = …; static SUNXI_CCU_DIV_TABLE(apb_clk, "apb", "ahb", 0x054, 8, 2, apb_div_table, 0); static SUNXI_CCU_GATE(bus_dma_clk, "bus-dma", "ahb", 0x060, BIT(6), 0); static SUNXI_CCU_GATE(bus_mmc0_clk, "bus-mmc0", "ahb", 0x060, BIT(8), 0); static SUNXI_CCU_GATE(bus_mmc1_clk, "bus-mmc1", "ahb", 0x060, BIT(9), 0); static SUNXI_CCU_GATE(bus_dram_clk, "bus-dram", "ahb", 0x060, BIT(14), 0); static SUNXI_CCU_GATE(bus_spi0_clk, "bus-spi0", "ahb", 0x060, BIT(20), 0); static SUNXI_CCU_GATE(bus_spi1_clk, "bus-spi1", "ahb", 0x060, BIT(21), 0); static SUNXI_CCU_GATE(bus_otg_clk, "bus-otg", "ahb", 0x060, BIT(24), 0); static SUNXI_CCU_GATE(bus_ve_clk, "bus-ve", "ahb", 0x064, BIT(0), 0); static SUNXI_CCU_GATE(bus_lcd_clk, "bus-lcd", "ahb", 0x064, BIT(4), 0); static SUNXI_CCU_GATE(bus_deinterlace_clk, "bus-deinterlace", "ahb", 0x064, BIT(5), 0); static SUNXI_CCU_GATE(bus_csi_clk, "bus-csi", "ahb", 0x064, BIT(8), 0); static SUNXI_CCU_GATE(bus_tvd_clk, "bus-tvd", "ahb", 0x064, BIT(9), 0); static SUNXI_CCU_GATE(bus_tve_clk, "bus-tve", "ahb", 0x064, BIT(10), 0); static SUNXI_CCU_GATE(bus_de_be_clk, "bus-de-be", "ahb", 0x064, BIT(12), 0); static SUNXI_CCU_GATE(bus_de_fe_clk, "bus-de-fe", "ahb", 0x064, BIT(14), 0); static SUNXI_CCU_GATE(bus_codec_clk, "bus-codec", "apb", 0x068, BIT(0), 0); static SUNXI_CCU_GATE(bus_spdif_clk, "bus-spdif", "apb", 0x068, BIT(1), 0); static SUNXI_CCU_GATE(bus_ir_clk, "bus-ir", "apb", 0x068, BIT(2), 0); static SUNXI_CCU_GATE(bus_rsb_clk, "bus-rsb", "apb", 0x068, BIT(3), 0); static SUNXI_CCU_GATE(bus_i2s0_clk, "bus-i2s0", "apb", 0x068, BIT(12), 0); static SUNXI_CCU_GATE(bus_i2c0_clk, "bus-i2c0", "apb", 0x068, BIT(16), 0); static SUNXI_CCU_GATE(bus_i2c1_clk, "bus-i2c1", "apb", 0x068, BIT(17), 0); static SUNXI_CCU_GATE(bus_i2c2_clk, "bus-i2c2", "apb", 0x068, BIT(18), 0); static SUNXI_CCU_GATE(bus_pio_clk, "bus-pio", "apb", 0x068, BIT(19), 0); static SUNXI_CCU_GATE(bus_uart0_clk, "bus-uart0", "apb", 0x068, BIT(20), 0); static SUNXI_CCU_GATE(bus_uart1_clk, "bus-uart1", "apb", 0x068, BIT(21), 0); static SUNXI_CCU_GATE(bus_uart2_clk, "bus-uart2", "apb", 0x068, BIT(22), 0); static const char * const mod0_default_parents[] = …; static SUNXI_CCU_MP_WITH_MUX_GATE(mmc0_clk, "mmc0", mod0_default_parents, 0x088, 0, 4, /* M */ 16, 2, /* P */ 24, 2, /* mux */ BIT(31), /* gate */ 0); static SUNXI_CCU_PHASE(mmc0_sample_clk, "mmc0_sample", "mmc0", 0x088, 20, 3, 0); static SUNXI_CCU_PHASE(mmc0_output_clk, "mmc0_output", "mmc0", 0x088, 8, 3, 0); static SUNXI_CCU_MP_WITH_MUX_GATE(mmc1_clk, "mmc1", mod0_default_parents, 0x08c, 0, 4, /* M */ 16, 2, /* P */ 24, 2, /* mux */ BIT(31), /* gate */ 0); static SUNXI_CCU_PHASE(mmc1_sample_clk, "mmc1_sample", "mmc1", 0x08c, 20, 3, 0); static SUNXI_CCU_PHASE(mmc1_output_clk, "mmc1_output", "mmc1", 0x08c, 8, 3, 0); static const char * const i2s_spdif_parents[] = …; static SUNXI_CCU_MUX_WITH_GATE(i2s_clk, "i2s", i2s_spdif_parents, 0x0b0, 16, 2, BIT(31), 0); static SUNXI_CCU_MUX_WITH_GATE(spdif_clk, "spdif", i2s_spdif_parents, 0x0b4, 16, 2, BIT(31), 0); static const char * const ir_parents[] = …; static SUNXI_CCU_MP_WITH_MUX_GATE(ir_clk, "ir", ir_parents, 0x0b8, 0, 4, /* M */ 16, 2, /* P */ 24, 2, /* mux */ BIT(31), /* gate */ 0); static SUNXI_CCU_GATE(usb_phy0_clk, "usb-phy0", "osc24M", 0x0cc, BIT(1), 0); static SUNXI_CCU_GATE(dram_ve_clk, "dram-ve", "pll-ddr", 0x100, BIT(0), 0); static SUNXI_CCU_GATE(dram_csi_clk, "dram-csi", "pll-ddr", 0x100, BIT(1), 0); static SUNXI_CCU_GATE(dram_deinterlace_clk, "dram-deinterlace", "pll-ddr", 0x100, BIT(2), 0); static SUNXI_CCU_GATE(dram_tvd_clk, "dram-tvd", "pll-ddr", 0x100, BIT(3), 0); static SUNXI_CCU_GATE(dram_de_fe_clk, "dram-de-fe", "pll-ddr", 0x100, BIT(24), 0); static SUNXI_CCU_GATE(dram_de_be_clk, "dram-de-be", "pll-ddr", 0x100, BIT(26), 0); static const char * const de_parents[] = …; static const u8 de_table[] = …; static SUNXI_CCU_M_WITH_MUX_TABLE_GATE(de_be_clk, "de-be", de_parents, de_table, 0x104, 0, 4, 24, 3, BIT(31), 0); static SUNXI_CCU_M_WITH_MUX_TABLE_GATE(de_fe_clk, "de-fe", de_parents, de_table, 0x10c, 0, 4, 24, 3, BIT(31), 0); static const char * const tcon_parents[] = …; static const u8 tcon_table[] = …; static SUNXI_CCU_MUX_TABLE_WITH_GATE(tcon_clk, "tcon", tcon_parents, tcon_table, 0x118, 24, 3, BIT(31), CLK_SET_RATE_PARENT); static const char * const deinterlace_parents[] = …; static const u8 deinterlace_table[] = …; static SUNXI_CCU_M_WITH_MUX_TABLE_GATE(deinterlace_clk, "deinterlace", deinterlace_parents, deinterlace_table, 0x11c, 0, 4, 24, 3, BIT(31), 0); static const char * const tve_clk2_parents[] = …; static const u8 tve_clk2_table[] = …; static SUNXI_CCU_M_WITH_MUX_TABLE_GATE(tve_clk2_clk, "tve-clk2", tve_clk2_parents, tve_clk2_table, 0x120, 0, 4, 24, 3, BIT(31), 0); static SUNXI_CCU_M_WITH_GATE(tve_clk1_clk, "tve-clk1", "tve-clk2", 0x120, 8, 1, BIT(15), 0); static const char * const tvd_parents[] = …; static SUNXI_CCU_M_WITH_MUX_GATE(tvd_clk, "tvd", tvd_parents, 0x124, 0, 4, 24, 3, BIT(31), 0); static const char * const csi_parents[] = …; static const u8 csi_table[] = …; static SUNXI_CCU_M_WITH_MUX_TABLE_GATE(csi_clk, "csi", csi_parents, csi_table, 0x120, 0, 4, 8, 3, BIT(15), 0); /* * TODO: BSP says the parent is pll-audio, however common sense and experience * told us it should be pll-ve. pll-ve is totally not used in BSP code. */ static SUNXI_CCU_GATE(ve_clk, "ve", "pll-audio", 0x13c, BIT(31), 0); static SUNXI_CCU_GATE(codec_clk, "codec", "pll-audio", 0x140, BIT(31), 0); static SUNXI_CCU_GATE(avs_clk, "avs", "osc24M", 0x144, BIT(31), 0); static struct ccu_common *suniv_ccu_clks[] = …; static const struct clk_hw *clk_parent_pll_audio[] = …; static CLK_FIXED_FACTOR_HWS(pll_audio_clk, "pll-audio", clk_parent_pll_audio, 4, 1, CLK_SET_RATE_PARENT); static CLK_FIXED_FACTOR_HWS(pll_audio_2x_clk, "pll-audio-2x", clk_parent_pll_audio, 2, 1, CLK_SET_RATE_PARENT); static CLK_FIXED_FACTOR_HWS(pll_audio_4x_clk, "pll-audio-4x", clk_parent_pll_audio, 1, 1, CLK_SET_RATE_PARENT); static CLK_FIXED_FACTOR_HWS(pll_audio_8x_clk, "pll-audio-8x", clk_parent_pll_audio, 1, 2, CLK_SET_RATE_PARENT); static CLK_FIXED_FACTOR_HW(pll_video_2x_clk, "pll-video-2x", &pll_video_clk.common.hw, 1, 2, 0); static struct clk_hw_onecell_data suniv_hw_clks = …; static struct ccu_reset_map suniv_ccu_resets[] = …; static const struct sunxi_ccu_desc suniv_ccu_desc = …; static struct ccu_pll_nb suniv_pll_cpu_nb = …; static struct ccu_mux_nb suniv_cpu_nb = …; static int suniv_f1c100s_ccu_probe(struct platform_device *pdev) { … } static const struct of_device_id suniv_f1c100s_ccu_ids[] = …; MODULE_DEVICE_TABLE(of, suniv_f1c100s_ccu_ids); static struct platform_driver suniv_f1c100s_ccu_driver = …; module_platform_driver(…) …; MODULE_IMPORT_NS(…); MODULE_DESCRIPTION(…) …; MODULE_LICENSE(…) …;
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