// SPDX-License-Identifier: GPL-2.0 /* * Exceptions for specific devices. Usually work-arounds for fatal design flaws. */ #include <linux/bitfield.h> #include <linux/delay.h> #include <linux/dmi.h> #include <linux/pci.h> #include <linux/suspend.h> #include <linux/vgaarb.h> #include <asm/amd_nb.h> #include <asm/hpet.h> #include <asm/pci_x86.h> static void pci_fixup_i450nx(struct pci_dev *d) { … } DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82451NX, pci_fixup_i450nx); static void pci_fixup_i450gx(struct pci_dev *d) { … } DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82454GX, pci_fixup_i450gx); static void pci_fixup_umc_ide(struct pci_dev *d) { … } DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_UMC, PCI_DEVICE_ID_UMC_UM8886BF, pci_fixup_umc_ide); static void pci_fixup_latency(struct pci_dev *d) { … } DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_5597, pci_fixup_latency); DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_5598, pci_fixup_latency); static void pci_fixup_piix4_acpi(struct pci_dev *d) { … } DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371AB_3, pci_fixup_piix4_acpi); /* * Addresses issues with problems in the memory write queue timer in * certain VIA Northbridges. This bugfix is per VIA's specifications, * except for the KL133/KM133: clearing bit 5 on those Northbridges seems * to trigger a bug in its integrated ProSavage video card, which * causes screen corruption. We only clear bits 6 and 7 for that chipset, * until VIA can provide us with definitive information on why screen * corruption occurs, and what exactly those bits do. * * VIA 8363,8622,8361 Northbridges: * - bits 5, 6, 7 at offset 0x55 need to be turned off * VIA 8367 (KT266x) Northbridges: * - bits 5, 6, 7 at offset 0x95 need to be turned off * VIA 8363 rev 0x81/0x84 (KL133/KM133) Northbridges: * - bits 6, 7 at offset 0x55 need to be turned off */ #define VIA_8363_KL133_REVISION_ID … #define VIA_8363_KM133_REVISION_ID … static void pci_fixup_via_northbridge_bug(struct pci_dev *d) { … } DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8363_0, pci_fixup_via_northbridge_bug); DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8622, pci_fixup_via_northbridge_bug); DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8361, pci_fixup_via_northbridge_bug); DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8367_0, pci_fixup_via_northbridge_bug); DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8363_0, pci_fixup_via_northbridge_bug); DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8622, pci_fixup_via_northbridge_bug); DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8361, pci_fixup_via_northbridge_bug); DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8367_0, pci_fixup_via_northbridge_bug); /* * For some reasons Intel decided that certain parts of their * 815, 845 and some other chipsets must look like PCI-to-PCI bridges * while they are obviously not. The 82801 family (AA, AB, BAM/CAM, * BA/CA/DB and E) PCI bridges are actually HUB-to-PCI ones, according * to Intel terminology. These devices do forward all addresses from * system to PCI bus no matter what are their window settings, so they are * "transparent" (or subtractive decoding) from programmers point of view. */ static void pci_fixup_transparent_bridge(struct pci_dev *dev) { … } DECLARE_PCI_FIXUP_CLASS_HEADER(PCI_VENDOR_ID_INTEL, PCI_ANY_ID, PCI_CLASS_BRIDGE_PCI, 8, pci_fixup_transparent_bridge); /* * Fixup for C1 Halt Disconnect problem on nForce2 systems. * * From information provided by "Allen Martin" <[email protected]>: * * A hang is caused when the CPU generates a very fast CONNECT/HALT cycle * sequence. Workaround is to set the SYSTEM_IDLE_TIMEOUT to 80 ns. * This allows the state-machine and timer to return to a proper state within * 80 ns of the CONNECT and probe appearing together. Since the CPU will not * issue another HALT within 80 ns of the initial HALT, the failure condition * is avoided. */ static void pci_fixup_nforce2(struct pci_dev *dev) { … } DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE2, pci_fixup_nforce2); DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE2, pci_fixup_nforce2); /* Max PCI Express root ports */ #define MAX_PCIEROOT … static int quirk_aspm_offset[MAX_PCIEROOT << 3]; #define GET_INDEX(a, b) … static int quirk_pcie_aspm_read(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 *value) { … } /* * Replace the original pci bus ops for write with a new one that will filter * the request to insure ASPM cannot be enabled. */ static int quirk_pcie_aspm_write(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 value) { … } static struct pci_ops quirk_pcie_aspm_ops = …; /* * Prevents PCI Express ASPM (Active State Power Management) being enabled. * * Save the register offset, where the ASPM control bits are located, * for each PCI Express device that is in the device list of * the root port in an array for fast indexing. Replace the bus ops * with the modified one. */ static void pcie_rootport_aspm_quirk(struct pci_dev *pdev) { … } DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_MCH_PA, pcie_rootport_aspm_quirk); DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_MCH_PA1, pcie_rootport_aspm_quirk); DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_MCH_PB, pcie_rootport_aspm_quirk); DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_MCH_PB1, pcie_rootport_aspm_quirk); DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_MCH_PC, pcie_rootport_aspm_quirk); DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_MCH_PC1, pcie_rootport_aspm_quirk); /* * Fixup to mark boot BIOS video selected by BIOS before it changes * * From information provided by "Jon Smirl" <[email protected]> * * The standard boot ROM sequence for an x86 machine uses the BIOS * to select an initial video card for boot display. This boot video * card will have its BIOS copied to 0xC0000 in system RAM. * IORESOURCE_ROM_SHADOW is used to associate the boot video * card with this copy. On laptops this copy has to be used since * the main ROM may be compressed or combined with another image. * See pci_map_rom() for use of this flag. Before marking the device * with IORESOURCE_ROM_SHADOW check if a vga_default_device is already set * by either arch code or vga-arbitration; if so only apply the fixup to this * already-determined primary video card. */ static void pci_fixup_video(struct pci_dev *pdev) { … } DECLARE_PCI_FIXUP_CLASS_HEADER(PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_DISPLAY_VGA, 8, pci_fixup_video); static const struct dmi_system_id msi_k8t_dmi_table[] = …; /* * The AMD-Athlon64 board MSI "K8T Neo2-FIR" disables the onboard sound * card if a PCI-soundcard is added. * * The BIOS only gives options "DISABLED" and "AUTO". This code sets * the corresponding register-value to enable the soundcard. * * The soundcard is only enabled, if the mainboard is identified * via DMI-tables and the soundcard is detected to be off. */ static void pci_fixup_msi_k8t_onboard_sound(struct pci_dev *dev) { … } DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, pci_fixup_msi_k8t_onboard_sound); DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, pci_fixup_msi_k8t_onboard_sound); /* * Some Toshiba laptops need extra code to enable their TI TSB43AB22/A. * * We pretend to bring them out of full D3 state, and restore the proper * IRQ, PCI cache line size, and BARs, otherwise the device won't function * properly. In some cases, the device will generate an interrupt on * the wrong IRQ line, causing any devices sharing the line it's * *supposed* to use to be disabled by the kernel's IRQ debug code. */ static u16 toshiba_line_size; static const struct dmi_system_id toshiba_ohci1394_dmi_table[] = …; static void pci_pre_fixup_toshiba_ohci1394(struct pci_dev *dev) { … } DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TI, 0x8032, pci_pre_fixup_toshiba_ohci1394); static void pci_post_fixup_toshiba_ohci1394(struct pci_dev *dev) { … } DECLARE_PCI_FIXUP_ENABLE(PCI_VENDOR_ID_TI, 0x8032, pci_post_fixup_toshiba_ohci1394); /* * Prevent the BIOS trapping accesses to the Cyrix CS5530A video device * configuration space. */ static void pci_early_fixup_cyrix_5530(struct pci_dev *dev) { … } DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_CYRIX, PCI_DEVICE_ID_CYRIX_5530_LEGACY, pci_early_fixup_cyrix_5530); DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_CYRIX, PCI_DEVICE_ID_CYRIX_5530_LEGACY, pci_early_fixup_cyrix_5530); /* * Siemens Nixdorf AG FSC Multiprocessor Interrupt Controller: * prevent update of the BAR0, which doesn't look like a normal BAR. */ static void pci_siemens_interrupt_controller(struct pci_dev *dev) { … } DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SIEMENS, 0x0015, pci_siemens_interrupt_controller); /* * SB600: Disable BAR1 on device 14.0 to avoid HPET resources from * confusing the PCI engine: */ static void sb600_disable_hpet_bar(struct pci_dev *dev) { … } DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_ATI, 0x4385, sb600_disable_hpet_bar); #ifdef CONFIG_HPET_TIMER static void sb600_hpet_quirk(struct pci_dev *dev) { … } DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATI, 0x4385, sb600_hpet_quirk); #endif /* * Twinhead H12Y needs us to block out a region otherwise we map devices * there and any access kills the box. * * See: https://bugzilla.kernel.org/show_bug.cgi?id=10231 * * Match off the LPC and svid/sdid (older kernels lose the bridge subvendor) */ static void twinhead_reserve_killing_zone(struct pci_dev *dev) { … } DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x27B9, twinhead_reserve_killing_zone); /* * Device [8086:2fc0] * Erratum HSE43 * CONFIG_TDP_NOMINAL CSR Implemented at Incorrect Offset * https://www.intel.com/content/www/us/en/processors/xeon/xeon-e5-v3-spec-update.html * * Devices [8086:6f60,6fa0,6fc0] * Erratum BDF2 * PCI BARs in the Home Agent Will Return Non-Zero Values During Enumeration * https://www.intel.com/content/www/us/en/processors/xeon/xeon-e5-v4-spec-update.html */ static void pci_invalid_bar(struct pci_dev *dev) { … } DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x2fc0, pci_invalid_bar); DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x6f60, pci_invalid_bar); DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x6fa0, pci_invalid_bar); DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x6fc0, pci_invalid_bar); DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0xa1ec, pci_invalid_bar); DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0xa1ed, pci_invalid_bar); DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0xa26c, pci_invalid_bar); DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0xa26d, pci_invalid_bar); /* * Device [1022:7808] * 23. USB Wake on Connect/Disconnect with Low Speed Devices * https://support.amd.com/TechDocs/46837.pdf * Appendix A2 * https://support.amd.com/TechDocs/42413.pdf */ static void pci_fixup_amd_ehci_pme(struct pci_dev *dev) { … } DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, 0x7808, pci_fixup_amd_ehci_pme); /* * Device [1022:7914] * When in D0, PME# doesn't get asserted when plugging USB 2.0 device. */ static void pci_fixup_amd_fch_xhci_pme(struct pci_dev *dev) { … } DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, 0x7914, pci_fixup_amd_fch_xhci_pme); /* * Apple MacBook Pro: Avoid [mem 0x7fa00000-0x7fbfffff] * * Using the [mem 0x7fa00000-0x7fbfffff] region, e.g., by assigning it to * the 00:1c.0 Root Port, causes a conflict with [io 0x1804], which is used * for soft poweroff and suspend-to-RAM. * * As far as we know, this is related to the address space, not to the Root * Port itself. Attaching the quirk to the Root Port is a convenience, but * it could probably also be a standalone DMI quirk. * * https://bugzilla.kernel.org/show_bug.cgi?id=103211 */ static void quirk_apple_mbp_poweroff(struct pci_dev *pdev) { … } DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x8c10, quirk_apple_mbp_poweroff); /* * VMD-enabled root ports will change the source ID for all messages * to the VMD device. Rather than doing device matching with the source * ID, the AER driver should traverse the child device tree, reading * AER registers to find the faulting device. */ static void quirk_no_aersid(struct pci_dev *pdev) { … } DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, PCI_ANY_ID, PCI_CLASS_BRIDGE_PCI, 8, quirk_no_aersid); static void quirk_intel_th_dnv(struct pci_dev *dev) { … } DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x19e1, quirk_intel_th_dnv); #ifdef CONFIG_PHYS_ADDR_T_64BIT #define AMD_141b_MMIO_BASE(x) … #define AMD_141b_MMIO_BASE_RE_MASK … #define AMD_141b_MMIO_BASE_WE_MASK … #define AMD_141b_MMIO_BASE_MMIOBASE_MASK … #define AMD_141b_MMIO_LIMIT(x) … #define AMD_141b_MMIO_LIMIT_MMIOLIMIT_MASK … #define AMD_141b_MMIO_HIGH(x) … #define AMD_141b_MMIO_HIGH_MMIOBASE_MASK … #define AMD_141b_MMIO_HIGH_MMIOLIMIT_SHIFT … #define AMD_141b_MMIO_HIGH_MMIOLIMIT_MASK … /* * The PCI Firmware Spec, rev 3.2, notes that ACPI should optionally allow * configuring host bridge windows using the _PRS and _SRS methods. * * But this is rarely implemented, so we manually enable a large 64bit BAR for * PCIe device on AMD Family 15h (Models 00h-1fh, 30h-3fh, 60h-7fh) Processors * here. */ static void pci_amd_enable_64bit_bar(struct pci_dev *dev) { … } DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, 0x1401, pci_amd_enable_64bit_bar); DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, 0x141b, pci_amd_enable_64bit_bar); DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, 0x1571, pci_amd_enable_64bit_bar); DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, 0x15b1, pci_amd_enable_64bit_bar); DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, 0x1601, pci_amd_enable_64bit_bar); DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_AMD, 0x1401, pci_amd_enable_64bit_bar); DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_AMD, 0x141b, pci_amd_enable_64bit_bar); DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_AMD, 0x1571, pci_amd_enable_64bit_bar); DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_AMD, 0x15b1, pci_amd_enable_64bit_bar); DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_AMD, 0x1601, pci_amd_enable_64bit_bar); #define RS690_LOWER_TOP_OF_DRAM2 … #define RS690_LOWER_TOP_OF_DRAM2_VALID … #define RS690_UPPER_TOP_OF_DRAM2 … #define RS690_HTIU_NB_INDEX … #define RS690_HTIU_NB_INDEX_WR_ENABLE … #define RS690_HTIU_NB_DATA … /* * Some BIOS implementations support RAM above 4GB, but do not configure the * PCI host to respond to bus master accesses for these addresses. These * implementations set the TOP_OF_DRAM_SLOT1 register correctly, so PCI DMA * works as expected for addresses below 4GB. * * Reference: "AMD RS690 ASIC Family Register Reference Guide" (pg. 2-57) * https://www.amd.com/system/files/TechDocs/43372_rs690_rrg_3.00o.pdf */ static void rs690_fix_64bit_dma(struct pci_dev *pdev) { … } DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x7910, rs690_fix_64bit_dma); #endif #ifdef CONFIG_AMD_NB #define AMD_15B8_RCC_DEV2_EPF0_STRAP2 … #define AMD_15B8_RCC_DEV2_EPF0_STRAP2_NO_SOFT_RESET_DEV2_F0_MASK … static void quirk_clear_strap_no_soft_reset_dev2_f0(struct pci_dev *dev) { … } DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, 0x15b8, quirk_clear_strap_no_soft_reset_dev2_f0); #endif /* * When returning from D3cold to D0, firmware on some Google Coral and Reef * family Chromebooks with Intel Apollo Lake SoC clobbers the headers of * both the L1 PM Substates capability and the previous capability for the * "Celeron N3350/Pentium N4200/Atom E3900 Series PCI Express Port B #1". * * Save those values at enumeration-time and restore them at resume. */ static u16 prev_cap, l1ss_cap; static u32 prev_header, l1ss_header; static void chromeos_save_apl_pci_l1ss_capability(struct pci_dev *dev) { … } static void chromeos_fixup_apl_pci_l1ss_capability(struct pci_dev *dev) { … } DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x5ad6, chromeos_save_apl_pci_l1ss_capability); DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, 0x5ad6, chromeos_fixup_apl_pci_l1ss_capability); /* * Disable D3cold on Asus B1400 PCI-NVMe bridge * * On this platform with VMD off, the NVMe device cannot successfully power * back on from D3cold. This appears to be an untested transition by the * vendor: Windows leaves the NVMe and parent bridge in D0 during suspend. * * We disable D3cold on the parent bridge for simplicity, and the fact that * both parent bridge and NVMe device share the same power resource. * * This is only needed on BIOS versions before 308; the newer versions flip * StorageD3Enable from 1 to 0. */ static const struct dmi_system_id asus_nvme_broken_d3cold_table[] = …; static void asus_disable_nvme_d3cold(struct pci_dev *pdev) { … } DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x9a09, asus_disable_nvme_d3cold); #ifdef CONFIG_SUSPEND /* * Root Ports on some AMD SoCs advertise PME_Support for D3hot and D3cold, but * if the SoC is put into a hardware sleep state by the amd-pmc driver, the * Root Ports don't generate wakeup interrupts for USB devices. * * When suspending, remove D3hot and D3cold from the PME_Support advertised * by the Root Port so we don't use those states if we're expecting wakeup * interrupts. Restore the advertised PME_Support when resuming. */ static void amd_rp_pme_suspend(struct pci_dev *dev) { … } static void amd_rp_pme_resume(struct pci_dev *dev) { … } /* Rembrandt (yellow_carp) */ DECLARE_PCI_FIXUP_SUSPEND(PCI_VENDOR_ID_AMD, 0x162e, amd_rp_pme_suspend); DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_AMD, 0x162e, amd_rp_pme_resume); DECLARE_PCI_FIXUP_SUSPEND(PCI_VENDOR_ID_AMD, 0x162f, amd_rp_pme_suspend); DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_AMD, 0x162f, amd_rp_pme_resume); /* Phoenix (pink_sardine) */ DECLARE_PCI_FIXUP_SUSPEND(PCI_VENDOR_ID_AMD, 0x1668, amd_rp_pme_suspend); DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_AMD, 0x1668, amd_rp_pme_resume); DECLARE_PCI_FIXUP_SUSPEND(PCI_VENDOR_ID_AMD, 0x1669, amd_rp_pme_suspend); DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_AMD, 0x1669, amd_rp_pme_resume); #endif /* CONFIG_SUSPEND */
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