// SPDX-License-Identifier: GPL-2.0 /* * Low-Level PCI Support for PC -- Routing of Interrupts * * (c) 1999--2000 Martin Mares <[email protected]> */ #include <linux/types.h> #include <linux/kernel.h> #include <linux/pci.h> #include <linux/init.h> #include <linux/interrupt.h> #include <linux/dmi.h> #include <linux/io.h> #include <linux/smp.h> #include <linux/spinlock.h> #include <asm/io_apic.h> #include <linux/irq.h> #include <linux/acpi.h> #include <asm/i8259.h> #include <asm/pc-conf-reg.h> #include <asm/pci_x86.h> #define PIRQ_SIGNATURE … #define PIRQ_VERSION … #define IRT_SIGNATURE … static int broken_hp_bios_irq9; static int acer_tm360_irqrouting; static struct irq_routing_table *pirq_table; static int pirq_enable_irq(struct pci_dev *dev); static void pirq_disable_irq(struct pci_dev *dev); /* * Never use: 0, 1, 2 (timer, keyboard, and cascade) * Avoid using: 13, 14 and 15 (FP error and IDE). * Penalize: 3, 4, 6, 7, 12 (known ISA uses: serial, floppy, parallel and mouse) */ unsigned int pcibios_irq_mask = …; static int pirq_penalty[16] = …; struct irq_router { … }; struct irq_router_handler { … }; int (*pcibios_enable_irq)(struct pci_dev *dev) = …; void (*pcibios_disable_irq)(struct pci_dev *dev) = …; /* * Check passed address for the PCI IRQ Routing Table signature * and perform checksum verification. */ static inline struct irq_routing_table *pirq_check_routing_table(u8 *addr, u8 *limit) { … } /* * Handle the $IRT PCI IRQ Routing Table format used by AMI for its BCP * (BIOS Configuration Program) external tool meant for tweaking BIOS * structures without the need to rebuild it from sources. The $IRT * format has been invented by AMI before Microsoft has come up with its * $PIR format and a $IRT table is therefore there in some systems that * lack a $PIR table. * * It uses the same PCI BIOS 2.1 format for interrupt routing entries * themselves but has a different simpler header prepended instead, * occupying 8 bytes, where a `$IRT' signature is followed by one byte * specifying the total number of interrupt routing entries allocated in * the table, then one byte specifying the actual number of entries used * (which the BCP tool can take advantage of when modifying the table), * and finally a 16-bit word giving the IRQs devoted exclusively to PCI. * Unlike with the $PIR table there is no alignment guarantee. * * Given the similarity of the two formats the $IRT one is trivial to * convert to the $PIR one, which we do here, except that obviously we * have no information as to the router device to use, but we can handle * it by matching PCI device IDs actually seen on the bus against ones * that our individual routers recognise. * * Reportedly there is another $IRT table format where a 16-bit word * follows the header instead that points to interrupt routing entries * in a $PIR table provided elsewhere. In that case this code will not * be reached though as the $PIR table will have been chosen instead. */ static inline struct irq_routing_table *pirq_convert_irt_table(u8 *addr, u8 *limit) { … } /* * Search 0xf0000 -- 0xfffff for the PCI IRQ Routing Table. */ static struct irq_routing_table * __init pirq_find_routing_table(void) { … } /* * If we have a IRQ routing table, use it to search for peer host * bridges. It's a gross hack, but since there are no other known * ways how to get a list of buses, we have to go this way. */ static void __init pirq_peer_trick(void) { … } /* * Code for querying and setting of IRQ routes on various interrupt routers. * PIC Edge/Level Control Registers (ELCR) 0x4d0 & 0x4d1. */ void elcr_set_level_irq(unsigned int irq) { … } /* * PIRQ routing for the M1487 ISA Bus Controller (IBC) ASIC used * with the ALi FinALi 486 chipset. The IBC is not decoded in the * PCI configuration space, so we identify it by the accompanying * M1489 Cache-Memory PCI Controller (CMP) ASIC. * * There are four 4-bit mappings provided, spread across two PCI * INTx Routing Table Mapping Registers, available in the port I/O * space accessible indirectly via the index/data register pair at * 0x22/0x23, located at indices 0x42 and 0x43 for the INT1/INT2 * and INT3/INT4 lines respectively. The INT1/INT3 and INT2/INT4 * lines are mapped in the low and the high 4-bit nibble of the * corresponding register as follows: * * 0000 : Disabled * 0001 : IRQ9 * 0010 : IRQ3 * 0011 : IRQ10 * 0100 : IRQ4 * 0101 : IRQ5 * 0110 : IRQ7 * 0111 : IRQ6 * 1000 : Reserved * 1001 : IRQ11 * 1010 : Reserved * 1011 : IRQ12 * 1100 : Reserved * 1101 : IRQ14 * 1110 : Reserved * 1111 : IRQ15 * * In addition to the usual ELCR register pair there is a separate * PCI INTx Sensitivity Register at index 0x44 in the same port I/O * space, whose bits 3:0 select the trigger mode for INT[4:1] lines * respectively. Any bit set to 1 causes interrupts coming on the * corresponding line to be passed to ISA as edge-triggered and * otherwise they are passed as level-triggered. Manufacturer's * documentation says this register has to be set consistently with * the relevant ELCR register. * * Accesses to the port I/O space concerned here need to be unlocked * by writing the value of 0xc5 to the Lock Register at index 0x03 * beforehand. Any other value written to said register prevents * further accesses from reaching the register file, except for the * Lock Register being written with 0xc5 again. * * References: * * "M1489/M1487: 486 PCI Chip Set", Version 1.2, Acer Laboratories * Inc., July 1997 */ #define PC_CONF_FINALI_LOCK … #define PC_CONF_FINALI_PCI_INTX_RT1 … #define PC_CONF_FINALI_PCI_INTX_RT2 … #define PC_CONF_FINALI_PCI_INTX_SENS … #define PC_CONF_FINALI_LOCK_KEY … static u8 read_pc_conf_nybble(u8 base, u8 index) { … } static void write_pc_conf_nybble(u8 base, u8 index, u8 val) { … } /* * FinALi pirq rules are as follows: * * - bit 0 selects between INTx Routing Table Mapping Registers, * * - bit 3 selects the nibble within the INTx Routing Table Mapping Register, * * - bits 7:4 map to bits 3:0 of the PCI INTx Sensitivity Register. */ static int pirq_finali_get(struct pci_dev *router, struct pci_dev *dev, int pirq) { … } static int pirq_finali_set(struct pci_dev *router, struct pci_dev *dev, int pirq, int irq) { … } static int pirq_finali_lvl(struct pci_dev *router, struct pci_dev *dev, int pirq, int irq) { … } /* * Common IRQ routing practice: nibbles in config space, * offset by some magic constant. */ static unsigned int read_config_nybble(struct pci_dev *router, unsigned offset, unsigned nr) { … } static void write_config_nybble(struct pci_dev *router, unsigned offset, unsigned nr, unsigned int val) { … } /* * ALI pirq entries are damn ugly, and completely undocumented. * This has been figured out from pirq tables, and it's not a pretty * picture. */ static int pirq_ali_get(struct pci_dev *router, struct pci_dev *dev, int pirq) { … } static int pirq_ali_set(struct pci_dev *router, struct pci_dev *dev, int pirq, int irq) { … } /* * PIRQ routing for the 82374EB/82374SB EISA System Component (ESC) * ASIC used with the Intel 82420 and 82430 PCIsets. The ESC is not * decoded in the PCI configuration space, so we identify it by the * accompanying 82375EB/82375SB PCI-EISA Bridge (PCEB) ASIC. * * There are four PIRQ Route Control registers, available in the * port I/O space accessible indirectly via the index/data register * pair at 0x22/0x23, located at indices 0x60/0x61/0x62/0x63 for the * PIRQ0/1/2/3# lines respectively. The semantics is the same as * with the PIIX router. * * Accesses to the port I/O space concerned here need to be unlocked * by writing the value of 0x0f to the ESC ID Register at index 0x02 * beforehand. Any other value written to said register prevents * further accesses from reaching the register file, except for the * ESC ID Register being written with 0x0f again. * * References: * * "82374EB/82374SB EISA System Component (ESC)", Intel Corporation, * Order Number: 290476-004, March 1996 * * "82375EB/82375SB PCI-EISA Bridge (PCEB)", Intel Corporation, Order * Number: 290477-004, March 1996 */ #define PC_CONF_I82374_ESC_ID … #define PC_CONF_I82374_PIRQ_ROUTE_CONTROL … #define PC_CONF_I82374_ESC_ID_KEY … static int pirq_esc_get(struct pci_dev *router, struct pci_dev *dev, int pirq) { … } static int pirq_esc_set(struct pci_dev *router, struct pci_dev *dev, int pirq, int irq) { … } /* * The Intel PIIX4 pirq rules are fairly simple: "pirq" is * just a pointer to the config space. */ static int pirq_piix_get(struct pci_dev *router, struct pci_dev *dev, int pirq) { … } static int pirq_piix_set(struct pci_dev *router, struct pci_dev *dev, int pirq, int irq) { … } /* * PIRQ routing for the 82426EX ISA Bridge (IB) ASIC used with the * Intel 82420EX PCIset. * * There are only two PIRQ Route Control registers, available in the * combined 82425EX/82426EX PCI configuration space, at 0x66 and 0x67 * for the PIRQ0# and PIRQ1# lines respectively. The semantics is * the same as with the PIIX router. * * References: * * "82420EX PCIset Data Sheet, 82425EX PCI System Controller (PSC) * and 82426EX ISA Bridge (IB)", Intel Corporation, Order Number: * 290488-004, December 1995 */ #define PCI_I82426EX_PIRQ_ROUTE_CONTROL … static int pirq_ib_get(struct pci_dev *router, struct pci_dev *dev, int pirq) { … } static int pirq_ib_set(struct pci_dev *router, struct pci_dev *dev, int pirq, int irq) { … } /* * The VIA pirq rules are nibble-based, like ALI, * but without the ugly irq number munging. * However, PIRQD is in the upper instead of lower 4 bits. */ static int pirq_via_get(struct pci_dev *router, struct pci_dev *dev, int pirq) { … } static int pirq_via_set(struct pci_dev *router, struct pci_dev *dev, int pirq, int irq) { … } /* * The VIA pirq rules are nibble-based, like ALI, * but without the ugly irq number munging. * However, for 82C586, nibble map is different . */ static int pirq_via586_get(struct pci_dev *router, struct pci_dev *dev, int pirq) { … } static int pirq_via586_set(struct pci_dev *router, struct pci_dev *dev, int pirq, int irq) { … } /* * ITE 8330G pirq rules are nibble-based * FIXME: pirqmap may be { 1, 0, 3, 2 }, * 2+3 are both mapped to irq 9 on my system */ static int pirq_ite_get(struct pci_dev *router, struct pci_dev *dev, int pirq) { … } static int pirq_ite_set(struct pci_dev *router, struct pci_dev *dev, int pirq, int irq) { … } /* * OPTI: high four bits are nibble pointer.. * I wonder what the low bits do? */ static int pirq_opti_get(struct pci_dev *router, struct pci_dev *dev, int pirq) { … } static int pirq_opti_set(struct pci_dev *router, struct pci_dev *dev, int pirq, int irq) { … } /* * Cyrix: nibble offset 0x5C * 0x5C bits 7:4 is INTB bits 3:0 is INTA * 0x5D bits 7:4 is INTD bits 3:0 is INTC */ static int pirq_cyrix_get(struct pci_dev *router, struct pci_dev *dev, int pirq) { … } static int pirq_cyrix_set(struct pci_dev *router, struct pci_dev *dev, int pirq, int irq) { … } /* * PIRQ routing for the SiS85C497 AT Bus Controller & Megacell (ATM) * ISA bridge used with the SiS 85C496/497 486 Green PC VESA/ISA/PCI * Chipset. * * There are four PCI INTx#-to-IRQ Link registers provided in the * SiS85C497 part of the peculiar combined 85C496/497 configuration * space decoded by the SiS85C496 PCI & CPU Memory Controller (PCM) * host bridge, at 0xc0/0xc1/0xc2/0xc3 respectively for the PCI INT * A/B/C/D lines. Bit 7 enables the respective link if set and bits * 3:0 select the 8259A IRQ line as follows: * * 0000 : Reserved * 0001 : Reserved * 0010 : Reserved * 0011 : IRQ3 * 0100 : IRQ4 * 0101 : IRQ5 * 0110 : IRQ6 * 0111 : IRQ7 * 1000 : Reserved * 1001 : IRQ9 * 1010 : IRQ10 * 1011 : IRQ11 * 1100 : IRQ12 * 1101 : Reserved * 1110 : IRQ14 * 1111 : IRQ15 * * We avoid using a reserved value for disabled links, hence the * choice of IRQ15 for that case. * * References: * * "486 Green PC VESA/ISA/PCI Chipset, SiS 85C496/497", Rev 3.0, * Silicon Integrated Systems Corp., July 1995 */ #define PCI_SIS497_INTA_TO_IRQ_LINK … #define PIRQ_SIS497_IRQ_MASK … #define PIRQ_SIS497_IRQ_ENABLE … static int pirq_sis497_get(struct pci_dev *router, struct pci_dev *dev, int pirq) { … } static int pirq_sis497_set(struct pci_dev *router, struct pci_dev *dev, int pirq, int irq) { … } /* * PIRQ routing for SiS 85C503 router used in several SiS chipsets. * We have to deal with the following issues here: * - vendors have different ideas about the meaning of link values * - some onboard devices (integrated in the chipset) have special * links and are thus routed differently (i.e. not via PCI INTA-INTD) * - different revision of the router have a different layout for * the routing registers, particularly for the onchip devices * * For all routing registers the common thing is we have one byte * per routeable link which is defined as: * bit 7 IRQ mapping enabled (0) or disabled (1) * bits [6:4] reserved (sometimes used for onchip devices) * bits [3:0] IRQ to map to * allowed: 3-7, 9-12, 14-15 * reserved: 0, 1, 2, 8, 13 * * The config-space registers located at 0x41/0x42/0x43/0x44 are * always used to route the normal PCI INT A/B/C/D respectively. * Apparently there are systems implementing PCI routing table using * link values 0x01-0x04 and others using 0x41-0x44 for PCI INTA..D. * We try our best to handle both link mappings. * * Currently (2003-05-21) it appears most SiS chipsets follow the * definition of routing registers from the SiS-5595 southbridge. * According to the SiS 5595 datasheets the revision id's of the * router (ISA-bridge) should be 0x01 or 0xb0. * * Furthermore we've also seen lspci dumps with revision 0x00 and 0xb1. * Looks like these are used in a number of SiS 5xx/6xx/7xx chipsets. * They seem to work with the current routing code. However there is * some concern because of the two USB-OHCI HCs (original SiS 5595 * had only one). YMMV. * * Onchip routing for router rev-id 0x01/0xb0 and probably 0x00/0xb1: * * 0x61: IDEIRQ: * bits [6:5] must be written 01 * bit 4 channel-select primary (0), secondary (1) * * 0x62: USBIRQ: * bit 6 OHCI function disabled (0), enabled (1) * * 0x6a: ACPI/SCI IRQ: bits 4-6 reserved * * 0x7e: Data Acq. Module IRQ - bits 4-6 reserved * * We support USBIRQ (in addition to INTA-INTD) and keep the * IDE, ACPI and DAQ routing untouched as set by the BIOS. * * Currently the only reported exception is the new SiS 65x chipset * which includes the SiS 69x southbridge. Here we have the 85C503 * router revision 0x04 and there are changes in the register layout * mostly related to the different USB HCs with USB 2.0 support. * * Onchip routing for router rev-id 0x04 (try-and-error observation) * * 0x60/0x61/0x62/0x63: 1xEHCI and 3xOHCI (companion) USB-HCs * bit 6-4 are probably unused, not like 5595 */ #define PIRQ_SIS503_IRQ_MASK … #define PIRQ_SIS503_IRQ_DISABLE … #define PIRQ_SIS503_USB_ENABLE … static int pirq_sis503_get(struct pci_dev *router, struct pci_dev *dev, int pirq) { … } static int pirq_sis503_set(struct pci_dev *router, struct pci_dev *dev, int pirq, int irq) { … } /* * VLSI: nibble offset 0x74 - educated guess due to routing table and * config space of VLSI 82C534 PCI-bridge/router (1004:0102) * Tested on HP OmniBook 800 covering PIRQ 1, 2, 4, 8 for onboard * devices, PIRQ 3 for non-pci(!) soundchip and (untested) PIRQ 6 * for the busbridge to the docking station. */ static int pirq_vlsi_get(struct pci_dev *router, struct pci_dev *dev, int pirq) { … } static int pirq_vlsi_set(struct pci_dev *router, struct pci_dev *dev, int pirq, int irq) { … } /* * ServerWorks: PCI interrupts mapped to system IRQ lines through Index * and Redirect I/O registers (0x0c00 and 0x0c01). The Index register * format is (PCIIRQ## | 0x10), e.g.: PCIIRQ10=0x1a. The Redirect * register is a straight binary coding of desired PIC IRQ (low nibble). * * The 'link' value in the PIRQ table is already in the correct format * for the Index register. There are some special index values: * 0x00 for ACPI (SCI), 0x01 for USB, 0x02 for IDE0, 0x04 for IDE1, * and 0x03 for SMBus. */ static int pirq_serverworks_get(struct pci_dev *router, struct pci_dev *dev, int pirq) { … } static int pirq_serverworks_set(struct pci_dev *router, struct pci_dev *dev, int pirq, int irq) { … } /* Support for AMD756 PCI IRQ Routing * Jhon H. Caicedo <[email protected]> * Jun/21/2001 0.2.0 Release, fixed to use "nybble" functions... (jhcaiced) * Jun/19/2001 Alpha Release 0.1.0 (jhcaiced) * The AMD756 pirq rules are nibble-based * offset 0x56 0-3 PIRQA 4-7 PIRQB * offset 0x57 0-3 PIRQC 4-7 PIRQD */ static int pirq_amd756_get(struct pci_dev *router, struct pci_dev *dev, int pirq) { … } static int pirq_amd756_set(struct pci_dev *router, struct pci_dev *dev, int pirq, int irq) { … } /* * PicoPower PT86C523 */ static int pirq_pico_get(struct pci_dev *router, struct pci_dev *dev, int pirq) { … } static int pirq_pico_set(struct pci_dev *router, struct pci_dev *dev, int pirq, int irq) { … } #ifdef CONFIG_PCI_BIOS static int pirq_bios_set(struct pci_dev *router, struct pci_dev *dev, int pirq, int irq) { struct pci_dev *bridge; int pin = pci_get_interrupt_pin(dev, &bridge); return pcibios_set_irq_routing(bridge, pin - 1, irq); } #endif static __init int intel_router_probe(struct irq_router *r, struct pci_dev *router, u16 device) { … } static __init int via_router_probe(struct irq_router *r, struct pci_dev *router, u16 device) { … } static __init int vlsi_router_probe(struct irq_router *r, struct pci_dev *router, u16 device) { … } static __init int serverworks_router_probe(struct irq_router *r, struct pci_dev *router, u16 device) { … } static __init int sis_router_probe(struct irq_router *r, struct pci_dev *router, u16 device) { … } static __init int cyrix_router_probe(struct irq_router *r, struct pci_dev *router, u16 device) { … } static __init int opti_router_probe(struct irq_router *r, struct pci_dev *router, u16 device) { … } static __init int ite_router_probe(struct irq_router *r, struct pci_dev *router, u16 device) { … } static __init int ali_router_probe(struct irq_router *r, struct pci_dev *router, u16 device) { … } static __init int amd_router_probe(struct irq_router *r, struct pci_dev *router, u16 device) { … } static __init int pico_router_probe(struct irq_router *r, struct pci_dev *router, u16 device) { … } static __initdata struct irq_router_handler pirq_routers[] = …; static struct irq_router pirq_router; static struct pci_dev *pirq_router_dev; /* * FIXME: should we have an option to say "generic for * chipset" ? */ static bool __init pirq_try_router(struct irq_router *r, struct irq_routing_table *rt, struct pci_dev *dev) { … } static void __init pirq_find_router(struct irq_router *r) { … } /* * We're supposed to match on the PCI device only and not the function, * but some BIOSes build their tables with the PCI function included * for motherboard devices, so if a complete match is found, then give * it precedence over a slot match. */ static struct irq_info *pirq_get_dev_info(struct pci_dev *dev) { … } /* * Buses behind bridges are typically not listed in the PIRQ routing table. * Do the usual dance then and walk the tree of bridges up adjusting the * pin number accordingly on the way until the originating root bus device * has been reached and then use its routing information. */ static struct irq_info *pirq_get_info(struct pci_dev *dev, u8 *pin) { … } static int pcibios_lookup_irq(struct pci_dev *dev, int assign) { … } void __init pcibios_fixup_irqs(void) { … } /* * Work around broken HP Pavilion Notebooks which assign USB to * IRQ 9 even though it is actually wired to IRQ 11 */ static int __init fix_broken_hp_bios_irq9(const struct dmi_system_id *d) { … } /* * Work around broken Acer TravelMate 360 Notebooks which assign * Cardbus to IRQ 11 even though it is actually wired to IRQ 10 */ static int __init fix_acer_tm360_irqrouting(const struct dmi_system_id *d) { … } static const struct dmi_system_id pciirq_dmi_table[] __initconst = …; void __init pcibios_irq_init(void) { … } static void pirq_penalize_isa_irq(int irq, int active) { … } void pcibios_penalize_isa_irq(int irq, int active) { … } static int pirq_enable_irq(struct pci_dev *dev) { … } bool mp_should_keep_irq(struct device *dev) { … } static void pirq_disable_irq(struct pci_dev *dev) { … }
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