// SPDX-License-Identifier: GPL-2.0 /* * Copyright (c) 2017 Icenowy Zheng <[email protected]> */ #include <linux/clk-provider.h> #include <linux/module.h> #include <linux/of.h> #include <linux/platform_device.h> #include "ccu_common.h" #include "ccu_reset.h" #include "ccu_div.h" #include "ccu_gate.h" #include "ccu_mp.h" #include "ccu_nm.h" #include "ccu-sun50i-h6-r.h" /* * Information about AR100 and AHB/APB clocks in R_CCU are gathered from * clock definitions in the BSP source code. */ static const char * const ar100_r_apb2_parents[] = …; static const struct ccu_mux_var_prediv ar100_r_apb2_predivs[] = …; static struct ccu_div ar100_clk = …; static CLK_FIXED_FACTOR_HW(r_ahb_clk, "r-ahb", &ar100_clk.common.hw, 1, 1, 0); static SUNXI_CCU_M(r_apb1_clk, "r-apb1", "r-ahb", 0x00c, 0, 2, 0); static struct ccu_div r_apb2_clk = …; /* * Information about the gate/resets are gathered from the clock header file * in the BSP source code, although most of them are unused. The existence * of the hardware block is verified with "3.1 Memory Mapping" chapter in * "Allwinner H6 V200 User Manual V1.1"; and the parent APB buses are verified * with "3.3.2.1 System Bus Tree" chapter inthe same document. */ static SUNXI_CCU_GATE(r_apb1_timer_clk, "r-apb1-timer", "r-apb1", 0x11c, BIT(0), 0); static SUNXI_CCU_GATE(r_apb1_twd_clk, "r-apb1-twd", "r-apb1", 0x12c, BIT(0), 0); static SUNXI_CCU_GATE(r_apb1_pwm_clk, "r-apb1-pwm", "r-apb1", 0x13c, BIT(0), 0); static SUNXI_CCU_GATE(r_apb2_uart_clk, "r-apb2-uart", "r-apb2", 0x18c, BIT(0), 0); static SUNXI_CCU_GATE(r_apb2_i2c_clk, "r-apb2-i2c", "r-apb2", 0x19c, BIT(0), 0); static SUNXI_CCU_GATE(r_apb2_rsb_clk, "r-apb2-rsb", "r-apb2", 0x1bc, BIT(0), 0); static SUNXI_CCU_GATE(r_apb1_ir_clk, "r-apb1-ir", "r-apb1", 0x1cc, BIT(0), 0); static SUNXI_CCU_GATE(r_apb1_w1_clk, "r-apb1-w1", "r-apb1", 0x1ec, BIT(0), 0); static SUNXI_CCU_GATE(r_apb1_rtc_clk, "r-apb1-rtc", "r-apb1", 0x20c, BIT(0), CLK_IGNORE_UNUSED); /* Information of IR(RX) mod clock is gathered from BSP source code */ static const char * const r_mod0_default_parents[] = …; static SUNXI_CCU_MP_WITH_MUX_GATE(ir_clk, "ir", r_mod0_default_parents, 0x1c0, 0, 5, /* M */ 8, 2, /* P */ 24, 1, /* mux */ BIT(31), /* gate */ 0); /* * BSP didn't use the 1-wire function at all now, and the information about * this mod clock is guessed from the IR mod clock above. The existence of * this mod clock is proven by BSP clock header, and the dividers are verified * by contents in the 1-wire related chapter of the User Manual. */ static SUNXI_CCU_MP_WITH_MUX_GATE(w1_clk, "w1", r_mod0_default_parents, 0x1e0, 0, 5, /* M */ 8, 2, /* P */ 24, 1, /* mux */ BIT(31), /* gate */ 0); static struct ccu_common *sun50i_h6_r_ccu_clks[] = …; static struct clk_hw_onecell_data sun50i_h6_r_hw_clks = …; static struct clk_hw_onecell_data sun50i_h616_r_hw_clks = …; static struct ccu_reset_map sun50i_h6_r_ccu_resets[] = …; static struct ccu_reset_map sun50i_h616_r_ccu_resets[] = …; static const struct sunxi_ccu_desc sun50i_h6_r_ccu_desc = …; static const struct sunxi_ccu_desc sun50i_h616_r_ccu_desc = …; static int sun50i_h6_r_ccu_probe(struct platform_device *pdev) { … } static const struct of_device_id sun50i_h6_r_ccu_ids[] = …; MODULE_DEVICE_TABLE(of, sun50i_h6_r_ccu_ids); static struct platform_driver sun50i_h6_r_ccu_driver = …; module_platform_driver(…) …; MODULE_IMPORT_NS(…); MODULE_DESCRIPTION(…) …; MODULE_LICENSE(…) …;
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