/* SPDX-License-Identifier: GPL-2.0-or-later */ /* * Copyright 2016 Maxime Ripard * * Maxime Ripard <[email protected]> */ #ifndef _CCU_SUN5I_H_ #define _CCU_SUN5I_H_ #include <dt-bindings/clock/sun5i-ccu.h> #include <dt-bindings/reset/sun5i-ccu.h> /* The HOSC is exported */ #define CLK_PLL_CORE … #define CLK_PLL_AUDIO_BASE … #define CLK_PLL_AUDIO … #define CLK_PLL_AUDIO_2X … #define CLK_PLL_AUDIO_4X … #define CLK_PLL_AUDIO_8X … #define CLK_PLL_VIDEO0 … /* The PLL_VIDEO0_2X is exported for HDMI */ #define CLK_PLL_VE … #define CLK_PLL_DDR_BASE … #define CLK_PLL_DDR … #define CLK_PLL_DDR_OTHER … #define CLK_PLL_PERIPH … #define CLK_PLL_VIDEO1 … /* The PLL_VIDEO1_2X is exported for HDMI */ /* The CPU clock is exported */ #define CLK_AXI … #define CLK_AHB … #define CLK_APB0 … #define CLK_APB1 … #define CLK_DRAM_AXI … /* AHB gates are exported */ /* APB0 gates are exported */ /* APB1 gates are exported */ /* Modules clocks are exported */ /* USB clocks are exported */ /* GPS clock is exported */ /* DRAM gates are exported */ /* More display modules clocks are exported */ #define CLK_TCON_CH1_SCLK … /* The rest of the module clocks are exported */ #define CLK_NUMBER … #endif /* _CCU_SUN5I_H_ */
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