// SPDX-License-Identifier: GPL-2.0-only /* * Copyright (c) 2016 Maxime Ripard. All rights reserved. */ #include <linux/clk-provider.h> #include <linux/io.h> #include <linux/of_address.h> #include "ccu_common.h" #include "ccu_reset.h" #include "ccu_div.h" #include "ccu_gate.h" #include "ccu_mp.h" #include "ccu_mult.h" #include "ccu_nk.h" #include "ccu_nkm.h" #include "ccu_nkmp.h" #include "ccu_nm.h" #include "ccu_phase.h" #include "ccu_sdm.h" #include "ccu-sun5i.h" static struct ccu_nkmp pll_core_clk = …; /* * The Audio PLL is supposed to have 4 outputs: 3 fixed factors from * the base (2x, 4x and 8x), and one variable divider (the one true * pll audio). * * With sigma-delta modulation for fractional-N on the audio PLL, * we have to use specific dividers. This means the variable divider * can no longer be used, as the audio codec requests the exact clock * rates we support through this mechanism. So we now hard code the * variable divider to 1. This means the clock rates will no longer * match the clock names. */ #define SUN5I_PLL_AUDIO_REG … static struct ccu_sdm_setting pll_audio_sdm_table[] = …; static struct ccu_nm pll_audio_base_clk = …; static struct ccu_mult pll_video0_clk = …; static struct ccu_nkmp pll_ve_clk = …; static struct ccu_nk pll_ddr_base_clk = …; static SUNXI_CCU_M(pll_ddr_clk, "pll-ddr", "pll-ddr-base", 0x020, 0, 2, CLK_IS_CRITICAL); static struct ccu_div pll_ddr_other_clk = …; static struct ccu_nk pll_periph_clk = …; static struct ccu_mult pll_video1_clk = …; static SUNXI_CCU_GATE(hosc_clk, "hosc", "osc24M", 0x050, BIT(0), 0); #define SUN5I_AHB_REG … static const char * const cpu_parents[] = …; static const struct ccu_mux_fixed_prediv cpu_predivs[] = …; static struct ccu_mux cpu_clk = …; static SUNXI_CCU_M(axi_clk, "axi", "cpu", 0x054, 0, 2, 0); static const char * const ahb_parents[] = …; static const struct ccu_mux_fixed_prediv ahb_predivs[] = …; static struct ccu_div ahb_clk = …; static struct clk_div_table apb0_div_table[] = …; static SUNXI_CCU_DIV_TABLE(apb0_clk, "apb0", "ahb", 0x054, 8, 2, apb0_div_table, 0); static const char * const apb1_parents[] = …; static SUNXI_CCU_MP_WITH_MUX(apb1_clk, "apb1", apb1_parents, 0x058, 0, 5, /* M */ 16, 2, /* P */ 24, 2, /* mux */ 0); static SUNXI_CCU_GATE(axi_dram_clk, "axi-dram", "axi", 0x05c, BIT(0), 0); static SUNXI_CCU_GATE(ahb_otg_clk, "ahb-otg", "ahb", 0x060, BIT(0), 0); static SUNXI_CCU_GATE(ahb_ehci_clk, "ahb-ehci", "ahb", 0x060, BIT(1), 0); static SUNXI_CCU_GATE(ahb_ohci_clk, "ahb-ohci", "ahb", 0x060, BIT(2), 0); static SUNXI_CCU_GATE(ahb_ss_clk, "ahb-ss", "ahb", 0x060, BIT(5), 0); static SUNXI_CCU_GATE(ahb_dma_clk, "ahb-dma", "ahb", 0x060, BIT(6), 0); static SUNXI_CCU_GATE(ahb_bist_clk, "ahb-bist", "ahb", 0x060, BIT(7), 0); static SUNXI_CCU_GATE(ahb_mmc0_clk, "ahb-mmc0", "ahb", 0x060, BIT(8), 0); static SUNXI_CCU_GATE(ahb_mmc1_clk, "ahb-mmc1", "ahb", 0x060, BIT(9), 0); static SUNXI_CCU_GATE(ahb_mmc2_clk, "ahb-mmc2", "ahb", 0x060, BIT(10), 0); static SUNXI_CCU_GATE(ahb_nand_clk, "ahb-nand", "ahb", 0x060, BIT(13), 0); static SUNXI_CCU_GATE(ahb_sdram_clk, "ahb-sdram", "ahb", 0x060, BIT(14), CLK_IS_CRITICAL); static SUNXI_CCU_GATE(ahb_emac_clk, "ahb-emac", "ahb", 0x060, BIT(17), 0); static SUNXI_CCU_GATE(ahb_ts_clk, "ahb-ts", "ahb", 0x060, BIT(18), 0); static SUNXI_CCU_GATE(ahb_spi0_clk, "ahb-spi0", "ahb", 0x060, BIT(20), 0); static SUNXI_CCU_GATE(ahb_spi1_clk, "ahb-spi1", "ahb", 0x060, BIT(21), 0); static SUNXI_CCU_GATE(ahb_spi2_clk, "ahb-spi2", "ahb", 0x060, BIT(22), 0); static SUNXI_CCU_GATE(ahb_gps_clk, "ahb-gps", "ahb", 0x060, BIT(26), 0); static SUNXI_CCU_GATE(ahb_hstimer_clk, "ahb-hstimer", "ahb", 0x060, BIT(28), 0); static SUNXI_CCU_GATE(ahb_ve_clk, "ahb-ve", "ahb", 0x064, BIT(0), 0); static SUNXI_CCU_GATE(ahb_tve_clk, "ahb-tve", "ahb", 0x064, BIT(2), 0); static SUNXI_CCU_GATE(ahb_lcd_clk, "ahb-lcd", "ahb", 0x064, BIT(4), 0); static SUNXI_CCU_GATE(ahb_csi_clk, "ahb-csi", "ahb", 0x064, BIT(8), 0); static SUNXI_CCU_GATE(ahb_hdmi_clk, "ahb-hdmi", "ahb", 0x064, BIT(11), 0); static SUNXI_CCU_GATE(ahb_de_be_clk, "ahb-de-be", "ahb", 0x064, BIT(12), 0); static SUNXI_CCU_GATE(ahb_de_fe_clk, "ahb-de-fe", "ahb", 0x064, BIT(14), 0); static SUNXI_CCU_GATE(ahb_iep_clk, "ahb-iep", "ahb", 0x064, BIT(19), 0); static SUNXI_CCU_GATE(ahb_gpu_clk, "ahb-gpu", "ahb", 0x064, BIT(20), 0); static SUNXI_CCU_GATE(apb0_codec_clk, "apb0-codec", "apb0", 0x068, BIT(0), 0); static SUNXI_CCU_GATE(apb0_spdif_clk, "apb0-spdif", "apb0", 0x068, BIT(1), 0); static SUNXI_CCU_GATE(apb0_i2s_clk, "apb0-i2s", "apb0", 0x068, BIT(3), 0); static SUNXI_CCU_GATE(apb0_pio_clk, "apb0-pio", "apb0", 0x068, BIT(5), 0); static SUNXI_CCU_GATE(apb0_ir_clk, "apb0-ir", "apb0", 0x068, BIT(6), 0); static SUNXI_CCU_GATE(apb0_keypad_clk, "apb0-keypad", "apb0", 0x068, BIT(10), 0); static SUNXI_CCU_GATE(apb1_i2c0_clk, "apb1-i2c0", "apb1", 0x06c, BIT(0), 0); static SUNXI_CCU_GATE(apb1_i2c1_clk, "apb1-i2c1", "apb1", 0x06c, BIT(1), 0); static SUNXI_CCU_GATE(apb1_i2c2_clk, "apb1-i2c2", "apb1", 0x06c, BIT(2), 0); static SUNXI_CCU_GATE(apb1_uart0_clk, "apb1-uart0", "apb1", 0x06c, BIT(16), 0); static SUNXI_CCU_GATE(apb1_uart1_clk, "apb1-uart1", "apb1", 0x06c, BIT(17), 0); static SUNXI_CCU_GATE(apb1_uart2_clk, "apb1-uart2", "apb1", 0x06c, BIT(18), 0); static SUNXI_CCU_GATE(apb1_uart3_clk, "apb1-uart3", "apb1", 0x06c, BIT(19), 0); static const char * const mod0_default_parents[] = …; static SUNXI_CCU_MP_WITH_MUX_GATE(nand_clk, "nand", mod0_default_parents, 0x080, 0, 4, /* M */ 16, 2, /* P */ 24, 2, /* mux */ BIT(31), /* gate */ 0); static SUNXI_CCU_MP_WITH_MUX_GATE(mmc0_clk, "mmc0", mod0_default_parents, 0x088, 0, 4, /* M */ 16, 2, /* P */ 24, 2, /* mux */ BIT(31), /* gate */ 0); static SUNXI_CCU_MP_WITH_MUX_GATE(mmc1_clk, "mmc1", mod0_default_parents, 0x08c, 0, 4, /* M */ 16, 2, /* P */ 24, 2, /* mux */ BIT(31), /* gate */ 0); static SUNXI_CCU_MP_WITH_MUX_GATE(mmc2_clk, "mmc2", mod0_default_parents, 0x090, 0, 4, /* M */ 16, 2, /* P */ 24, 2, /* mux */ BIT(31), /* gate */ 0); static SUNXI_CCU_MP_WITH_MUX_GATE(ts_clk, "ts", mod0_default_parents, 0x098, 0, 4, /* M */ 16, 2, /* P */ 24, 2, /* mux */ BIT(31), /* gate */ 0); static SUNXI_CCU_MP_WITH_MUX_GATE(ss_clk, "ss", mod0_default_parents, 0x09c, 0, 4, /* M */ 16, 2, /* P */ 24, 2, /* mux */ BIT(31), /* gate */ 0); static SUNXI_CCU_MP_WITH_MUX_GATE(spi0_clk, "spi0", mod0_default_parents, 0x0a0, 0, 4, /* M */ 16, 2, /* P */ 24, 2, /* mux */ BIT(31), /* gate */ 0); static SUNXI_CCU_MP_WITH_MUX_GATE(spi1_clk, "spi1", mod0_default_parents, 0x0a4, 0, 4, /* M */ 16, 2, /* P */ 24, 2, /* mux */ BIT(31), /* gate */ 0); static SUNXI_CCU_MP_WITH_MUX_GATE(spi2_clk, "spi2", mod0_default_parents, 0x0a8, 0, 4, /* M */ 16, 2, /* P */ 24, 2, /* mux */ BIT(31), /* gate */ 0); static SUNXI_CCU_MP_WITH_MUX_GATE(ir_clk, "ir", mod0_default_parents, 0x0b0, 0, 4, /* M */ 16, 2, /* P */ 24, 2, /* mux */ BIT(31), /* gate */ 0); static const char * const i2s_parents[] = …; static SUNXI_CCU_MUX_WITH_GATE(i2s_clk, "i2s", i2s_parents, 0x0b8, 16, 2, BIT(31), CLK_SET_RATE_PARENT); static const char * const spdif_parents[] = …; static SUNXI_CCU_MUX_WITH_GATE(spdif_clk, "spdif", spdif_parents, 0x0c0, 16, 2, BIT(31), CLK_SET_RATE_PARENT); static const char * const keypad_parents[] = …; static const u8 keypad_table[] = …; static struct ccu_mp keypad_clk = …; static SUNXI_CCU_GATE(usb_ohci_clk, "usb-ohci", "pll-periph", 0x0cc, BIT(6), 0); static SUNXI_CCU_GATE(usb_phy0_clk, "usb-phy0", "pll-periph", 0x0cc, BIT(8), 0); static SUNXI_CCU_GATE(usb_phy1_clk, "usb-phy1", "pll-periph", 0x0cc, BIT(9), 0); static const char * const gps_parents[] = …; static SUNXI_CCU_M_WITH_MUX_GATE(gps_clk, "gps", gps_parents, 0x0d0, 0, 3, 24, 2, BIT(31), 0); static SUNXI_CCU_GATE(dram_ve_clk, "dram-ve", "pll-ddr", 0x100, BIT(0), 0); static SUNXI_CCU_GATE(dram_csi_clk, "dram-csi", "pll-ddr", 0x100, BIT(1), 0); static SUNXI_CCU_GATE(dram_ts_clk, "dram-ts", "pll-ddr", 0x100, BIT(3), 0); static SUNXI_CCU_GATE(dram_tve_clk, "dram-tve", "pll-ddr", 0x100, BIT(5), 0); static SUNXI_CCU_GATE(dram_de_fe_clk, "dram-de-fe", "pll-ddr", 0x100, BIT(25), 0); static SUNXI_CCU_GATE(dram_de_be_clk, "dram-de-be", "pll-ddr", 0x100, BIT(26), 0); static SUNXI_CCU_GATE(dram_ace_clk, "dram-ace", "pll-ddr", 0x100, BIT(29), 0); static SUNXI_CCU_GATE(dram_iep_clk, "dram-iep", "pll-ddr", 0x100, BIT(31), 0); static const char * const de_parents[] = …; static SUNXI_CCU_M_WITH_MUX_GATE(de_be_clk, "de-be", de_parents, 0x104, 0, 4, 24, 2, BIT(31), 0); static SUNXI_CCU_M_WITH_MUX_GATE(de_fe_clk, "de-fe", de_parents, 0x10c, 0, 4, 24, 2, BIT(31), 0); static const char * const tcon_parents[] = …; static SUNXI_CCU_MUX_WITH_GATE(tcon_ch0_clk, "tcon-ch0-sclk", tcon_parents, 0x118, 24, 2, BIT(31), CLK_SET_RATE_PARENT); static SUNXI_CCU_M_WITH_MUX_GATE(tcon_ch1_sclk2_clk, "tcon-ch1-sclk2", tcon_parents, 0x12c, 0, 4, 24, 2, BIT(31), CLK_SET_RATE_PARENT); static SUNXI_CCU_M_WITH_GATE(tcon_ch1_sclk1_clk, "tcon-ch1-sclk1", "tcon-ch1-sclk2", 0x12c, 11, 1, BIT(15), CLK_SET_RATE_PARENT); static const char * const csi_parents[] = …; static const u8 csi_table[] = …; static SUNXI_CCU_M_WITH_MUX_TABLE_GATE(csi_clk, "csi", csi_parents, csi_table, 0x134, 0, 5, 24, 3, BIT(31), 0); static SUNXI_CCU_GATE(ve_clk, "ve", "pll-ve", 0x13c, BIT(31), CLK_SET_RATE_PARENT); static SUNXI_CCU_GATE(codec_clk, "codec", "pll-audio", 0x140, BIT(31), CLK_SET_RATE_PARENT); static SUNXI_CCU_GATE(avs_clk, "avs", "hosc", 0x144, BIT(31), 0); static const char * const hdmi_parents[] = …; static const u8 hdmi_table[] = …; static SUNXI_CCU_M_WITH_MUX_TABLE_GATE(hdmi_clk, "hdmi", hdmi_parents, hdmi_table, 0x150, 0, 4, 24, 2, BIT(31), CLK_SET_RATE_PARENT); static const char * const gpu_parents[] = …; static SUNXI_CCU_M_WITH_MUX_GATE(gpu_clk, "gpu", gpu_parents, 0x154, 0, 4, 24, 3, BIT(31), 0); static const char * const mbus_parents[] = …; static SUNXI_CCU_MP_WITH_MUX_GATE(mbus_clk, "mbus", mbus_parents, 0x15c, 0, 4, 16, 2, 24, 2, BIT(31), CLK_IS_CRITICAL); static SUNXI_CCU_GATE(iep_clk, "iep", "de-be", 0x160, BIT(31), 0); static struct ccu_common *sun5i_a10s_ccu_clks[] = …; static const struct clk_hw *clk_parent_pll_audio[] = …; /* We hardcode the divider to 1 for now */ static CLK_FIXED_FACTOR_HWS(pll_audio_clk, "pll-audio", clk_parent_pll_audio, 1, 1, CLK_SET_RATE_PARENT); static CLK_FIXED_FACTOR_HWS(pll_audio_2x_clk, "pll-audio-2x", clk_parent_pll_audio, 2, 1, CLK_SET_RATE_PARENT); static CLK_FIXED_FACTOR_HWS(pll_audio_4x_clk, "pll-audio-4x", clk_parent_pll_audio, 1, 1, CLK_SET_RATE_PARENT); static CLK_FIXED_FACTOR_HWS(pll_audio_8x_clk, "pll-audio-8x", clk_parent_pll_audio, 1, 2, CLK_SET_RATE_PARENT); static CLK_FIXED_FACTOR_HW(pll_video0_2x_clk, "pll-video0-2x", &pll_video0_clk.common.hw, 1, 2, CLK_SET_RATE_PARENT); static CLK_FIXED_FACTOR_HW(pll_video1_2x_clk, "pll-video1-2x", &pll_video1_clk.common.hw, 1, 2, CLK_SET_RATE_PARENT); static struct clk_hw_onecell_data sun5i_a10s_hw_clks = …; static struct ccu_reset_map sun5i_a10s_ccu_resets[] = …; static const struct sunxi_ccu_desc sun5i_a10s_ccu_desc = …; /* * The A13 is the A10s minus the TS, GPS, HDMI, I2S and the keypad */ static struct clk_hw_onecell_data sun5i_a13_hw_clks = …; static const struct sunxi_ccu_desc sun5i_a13_ccu_desc = …; /* * The GR8 is the A10s CCU minus the HDMI and keypad, plus SPDIF */ static struct clk_hw_onecell_data sun5i_gr8_hw_clks = …; static const struct sunxi_ccu_desc sun5i_gr8_ccu_desc = …; static void __init sun5i_ccu_init(struct device_node *node, const struct sunxi_ccu_desc *desc) { … } static void __init sun5i_a10s_ccu_setup(struct device_node *node) { … } CLK_OF_DECLARE(sun5i_a10s_ccu, "allwinner,sun5i-a10s-ccu", sun5i_a10s_ccu_setup); static void __init sun5i_a13_ccu_setup(struct device_node *node) { … } CLK_OF_DECLARE(sun5i_a13_ccu, "allwinner,sun5i-a13-ccu", sun5i_a13_ccu_setup); static void __init sun5i_gr8_ccu_setup(struct device_node *node) { … } CLK_OF_DECLARE(sun5i_gr8_ccu, "nextthing,gr8-ccu", sun5i_gr8_ccu_setup);
Codebase Browser
linux