/* SPDX-License-Identifier: GPL-2.0-or-later */ /* * Copyright 2017 Priit Laes * * Priit Laes <[email protected]> */ #ifndef _CCU_SUN4I_A10_H_ #define _CCU_SUN4I_A10_H_ #include <dt-bindings/clock/sun4i-a10-ccu.h> #include <dt-bindings/clock/sun7i-a20-ccu.h> #include <dt-bindings/reset/sun4i-a10-ccu.h> /* The HOSC is exported */ #define CLK_PLL_CORE … #define CLK_PLL_AUDIO_BASE … #define CLK_PLL_AUDIO … #define CLK_PLL_AUDIO_2X … #define CLK_PLL_AUDIO_4X … #define CLK_PLL_AUDIO_8X … #define CLK_PLL_VIDEO0 … /* The PLL_VIDEO0_2X clock is exported */ #define CLK_PLL_VE … #define CLK_PLL_DDR_BASE … #define CLK_PLL_DDR … #define CLK_PLL_DDR_OTHER … #define CLK_PLL_PERIPH_BASE … #define CLK_PLL_PERIPH … #define CLK_PLL_PERIPH_SATA … #define CLK_PLL_VIDEO1 … /* The PLL_VIDEO1_2X clock is exported */ #define CLK_PLL_GPU … /* The CPU clock is exported */ #define CLK_AXI … #define CLK_AXI_DRAM … #define CLK_AHB … #define CLK_APB0 … #define CLK_APB1 … /* AHB gates are exported (23..68) */ /* APB0 gates are exported (69..78) */ /* APB1 gates are exported (79..95) */ /* IP module clocks are exported (96..128) */ /* DRAM gates are exported (129..142)*/ /* Media (display engine clocks & etc) are exported (143..169) */ #define CLK_NUMBER_SUN4I … #define CLK_NUMBER_SUN7I … #endif /* _CCU_SUN4I_A10_H_ */
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