linux/drivers/clk/sunxi-ng/ccu_mp.c

// SPDX-License-Identifier: GPL-2.0-or-later
/*
 * Copyright (C) 2016 Maxime Ripard
 * Maxime Ripard <[email protected]>
 */

#include <linux/clk-provider.h>
#include <linux/io.h>

#include "ccu_gate.h"
#include "ccu_mp.h"

static unsigned long ccu_mp_find_best(unsigned long parent, unsigned long rate,
				      unsigned int max_m, unsigned int max_p,
				      unsigned int *m, unsigned int *p)
{ … }

static unsigned long ccu_mp_find_best_with_parent_adj(struct clk_hw *hw,
						      unsigned long *parent,
						      unsigned long rate,
						      unsigned int max_m,
						      unsigned int max_p)
{ … }

static unsigned long ccu_mp_round_rate(struct ccu_mux_internal *mux,
				       struct clk_hw *hw,
				       unsigned long *parent_rate,
				       unsigned long rate,
				       void *data)
{ … }

static void ccu_mp_disable(struct clk_hw *hw)
{ … }

static int ccu_mp_enable(struct clk_hw *hw)
{ … }

static int ccu_mp_is_enabled(struct clk_hw *hw)
{ … }

static unsigned long ccu_mp_recalc_rate(struct clk_hw *hw,
					unsigned long parent_rate)
{ … }

static int ccu_mp_determine_rate(struct clk_hw *hw,
				 struct clk_rate_request *req)
{ … }

static int ccu_mp_set_rate(struct clk_hw *hw, unsigned long rate,
			   unsigned long parent_rate)
{ … }

static u8 ccu_mp_get_parent(struct clk_hw *hw)
{ … }

static int ccu_mp_set_parent(struct clk_hw *hw, u8 index)
{ … }

const struct clk_ops ccu_mp_ops = …;
EXPORT_SYMBOL_NS_GPL(…);

/*
 * Support for MMC timing mode switching
 *
 * The MMC clocks on some SoCs support switching between old and
 * new timing modes. A platform specific API is provided to query
 * and set the timing mode on supported SoCs.
 *
 * In addition, a special class of ccu_mp_ops is provided, which
 * takes in to account the timing mode switch. When the new timing
 * mode is active, the clock output rate is halved. This new class
 * is a wrapper around the generic ccu_mp_ops. When clock rates
 * are passed through to ccu_mp_ops callbacks, they are doubled
 * if the new timing mode bit is set, to account for the post
 * divider. Conversely, when clock rates are passed back, they
 * are halved if the mode bit is set.
 */

static unsigned long ccu_mp_mmc_recalc_rate(struct clk_hw *hw,
					    unsigned long parent_rate)
{ … }

static int ccu_mp_mmc_determine_rate(struct clk_hw *hw,
				     struct clk_rate_request *req)
{ … }

static int ccu_mp_mmc_set_rate(struct clk_hw *hw, unsigned long rate,
			       unsigned long parent_rate)
{ … }

const struct clk_ops ccu_mp_mmc_ops = …;
EXPORT_SYMBOL_NS_GPL(…);