// SPDX-License-Identifier: GPL-2.0 /* * Copyright (c) 2020 [email protected] * Copyright (C) 2021 Samuel Holland <[email protected]> */ #include <linux/clk-provider.h> #include <linux/io.h> #include <linux/module.h> #include <linux/platform_device.h> #include "../clk.h" #include "ccu_common.h" #include "ccu_reset.h" #include "ccu_div.h" #include "ccu_gate.h" #include "ccu_mp.h" #include "ccu_mult.h" #include "ccu_nk.h" #include "ccu_nkm.h" #include "ccu_nkmp.h" #include "ccu_nm.h" #include "ccu-sun20i-d1.h" static const struct clk_parent_data osc24M[] = …; /* * For the CPU PLL, the output divider is described as "only for testing" * in the user manual. So it's not modelled and forced to 0. */ #define SUN20I_D1_PLL_CPUX_REG … static struct ccu_mult pll_cpux_clk = …; /* Some PLLs are input * N / div1 / P. Model them as NKMP with no K */ #define SUN20I_D1_PLL_DDR0_REG … static struct ccu_nkmp pll_ddr0_clk = …; #define SUN20I_D1_PLL_PERIPH0_REG … static struct ccu_nm pll_periph0_4x_clk = …; static const struct clk_hw *pll_periph0_4x_hws[] = …; static SUNXI_CCU_M_HWS(pll_periph0_2x_clk, "pll-periph0-2x", pll_periph0_4x_hws, 0x020, 16, 3, 0); static SUNXI_CCU_M_HWS(pll_periph0_800M_clk, "pll-periph0-800M", pll_periph0_4x_hws, 0x020, 20, 3, 0); static const struct clk_hw *pll_periph0_2x_hws[] = …; static CLK_FIXED_FACTOR_HWS(pll_periph0_clk, "pll-periph0", pll_periph0_2x_hws, 2, 1, 0); static const struct clk_hw *pll_periph0_hws[] = …; static CLK_FIXED_FACTOR_HWS(pll_periph0_div3_clk, "pll-periph0-div3", pll_periph0_2x_hws, 6, 1, 0); /* * For Video PLLs, the output divider is described as "only for testing" * in the user manual. So it's not modelled and forced to 0. */ #define SUN20I_D1_PLL_VIDEO0_REG … static struct ccu_nm pll_video0_4x_clk = …; static const struct clk_hw *pll_video0_4x_hws[] = …; static CLK_FIXED_FACTOR_HWS(pll_video0_2x_clk, "pll-video0-2x", pll_video0_4x_hws, 2, 1, CLK_SET_RATE_PARENT); static CLK_FIXED_FACTOR_HWS(pll_video0_clk, "pll-video0", pll_video0_4x_hws, 4, 1, CLK_SET_RATE_PARENT); #define SUN20I_D1_PLL_VIDEO1_REG … static struct ccu_nm pll_video1_4x_clk = …; static const struct clk_hw *pll_video1_4x_hws[] = …; static CLK_FIXED_FACTOR_HWS(pll_video1_2x_clk, "pll-video1-2x", pll_video1_4x_hws, 2, 1, CLK_SET_RATE_PARENT); static CLK_FIXED_FACTOR_HWS(pll_video1_clk, "pll-video1", pll_video1_4x_hws, 4, 1, CLK_SET_RATE_PARENT); #define SUN20I_D1_PLL_VE_REG … static struct ccu_nkmp pll_ve_clk = …; /* * PLL_AUDIO0 has m0, m1 dividers in addition to the usual N, M factors. * Since we only need one frequency from this PLL (22.5792 x 4 == 90.3168 MHz), * ignore them for now. Enforce the default for them, which is m1 = 0, m0 = 0. * The M factor must be an even number to produce a 50% duty cycle output. */ #define SUN20I_D1_PLL_AUDIO0_REG … static struct ccu_sdm_setting pll_audio0_sdm_table[] = …; static struct ccu_nm pll_audio0_4x_clk = …; static const struct clk_hw *pll_audio0_4x_hws[] = …; static CLK_FIXED_FACTOR_HWS(pll_audio0_2x_clk, "pll-audio0-2x", pll_audio0_4x_hws, 2, 1, 0); static CLK_FIXED_FACTOR_HWS(pll_audio0_clk, "pll-audio0", pll_audio0_4x_hws, 4, 1, 0); /* * PLL_AUDIO1 doesn't need Fractional-N. The output is usually 614.4 MHz for * audio. The ADC or DAC should divide the PLL output further to 24.576 MHz. */ #define SUN20I_D1_PLL_AUDIO1_REG … static struct ccu_nm pll_audio1_clk = …; static const struct clk_hw *pll_audio1_hws[] = …; static SUNXI_CCU_M_HWS(pll_audio1_div2_clk, "pll-audio1-div2", pll_audio1_hws, 0x080, 16, 3, 0); static SUNXI_CCU_M_HWS(pll_audio1_div5_clk, "pll-audio1-div5", pll_audio1_hws, 0x080, 20, 3, 0); /* * The CPUX gate is not modelled - it is in a separate register (0x504) * and has a special key field. The clock does not need to be ungated anyway. */ static const struct clk_parent_data cpux_parents[] = …; static SUNXI_CCU_MUX_DATA(cpux_clk, "cpux", cpux_parents, 0x500, 24, 3, CLK_SET_RATE_PARENT | CLK_IS_CRITICAL); static const struct clk_hw *cpux_hws[] = …; static SUNXI_CCU_M_HWS(cpux_axi_clk, "cpux-axi", cpux_hws, 0x500, 0, 2, 0); static SUNXI_CCU_M_HWS(cpux_apb_clk, "cpux-apb", cpux_hws, 0x500, 8, 2, 0); static const struct clk_parent_data psi_ahb_parents[] = …; static SUNXI_CCU_MP_DATA_WITH_MUX(psi_ahb_clk, "psi-ahb", psi_ahb_parents, 0x510, 0, 2, /* M */ 8, 2, /* P */ 24, 2, /* mux */ 0); static const struct clk_parent_data apb0_apb1_parents[] = …; static SUNXI_CCU_MP_DATA_WITH_MUX(apb0_clk, "apb0", apb0_apb1_parents, 0x520, 0, 5, /* M */ 8, 2, /* P */ 24, 2, /* mux */ 0); static SUNXI_CCU_MP_DATA_WITH_MUX(apb1_clk, "apb1", apb0_apb1_parents, 0x524, 0, 5, /* M */ 8, 2, /* P */ 24, 2, /* mux */ 0); static const struct clk_hw *psi_ahb_hws[] = …; static const struct clk_hw *apb0_hws[] = …; static const struct clk_hw *apb1_hws[] = …; static const struct clk_hw *de_di_g2d_parents[] = …; static SUNXI_CCU_M_HW_WITH_MUX_GATE(de_clk, "de", de_di_g2d_parents, 0x600, 0, 5, /* M */ 24, 3, /* mux */ BIT(31), /* gate */ CLK_SET_RATE_PARENT); static SUNXI_CCU_GATE_HWS(bus_de_clk, "bus-de", psi_ahb_hws, 0x60c, BIT(0), 0); static SUNXI_CCU_M_HW_WITH_MUX_GATE(di_clk, "di", de_di_g2d_parents, 0x620, 0, 5, /* M */ 24, 3, /* mux */ BIT(31), /* gate */ CLK_SET_RATE_PARENT); static SUNXI_CCU_GATE_HWS(bus_di_clk, "bus-di", psi_ahb_hws, 0x62c, BIT(0), 0); static SUNXI_CCU_M_HW_WITH_MUX_GATE(g2d_clk, "g2d", de_di_g2d_parents, 0x630, 0, 5, /* M */ 24, 3, /* mux */ BIT(31), /* gate */ 0); static SUNXI_CCU_GATE_HWS(bus_g2d_clk, "bus-g2d", psi_ahb_hws, 0x63c, BIT(0), 0); static const struct clk_parent_data ce_parents[] = …; static SUNXI_CCU_MP_DATA_WITH_MUX_GATE(ce_clk, "ce", ce_parents, 0x680, 0, 4, /* M */ 8, 2, /* P */ 24, 3, /* mux */ BIT(31), /* gate */ 0); static SUNXI_CCU_GATE_HWS(bus_ce_clk, "bus-ce", psi_ahb_hws, 0x68c, BIT(0), 0); static const struct clk_hw *ve_parents[] = …; static SUNXI_CCU_M_HW_WITH_MUX_GATE(ve_clk, "ve", ve_parents, 0x690, 0, 5, /* M */ 24, 1, /* mux */ BIT(31), /* gate */ CLK_SET_RATE_PARENT); static SUNXI_CCU_GATE_HWS(bus_ve_clk, "bus-ve", psi_ahb_hws, 0x69c, BIT(0), 0); static SUNXI_CCU_GATE_HWS(bus_dma_clk, "bus-dma", psi_ahb_hws, 0x70c, BIT(0), 0); static SUNXI_CCU_GATE_HWS(bus_msgbox0_clk, "bus-msgbox0", psi_ahb_hws, 0x71c, BIT(0), 0); static SUNXI_CCU_GATE_HWS(bus_msgbox1_clk, "bus-msgbox1", psi_ahb_hws, 0x71c, BIT(1), 0); static SUNXI_CCU_GATE_HWS(bus_msgbox2_clk, "bus-msgbox2", psi_ahb_hws, 0x71c, BIT(2), 0); static SUNXI_CCU_GATE_HWS(bus_spinlock_clk, "bus-spinlock", psi_ahb_hws, 0x72c, BIT(0), 0); static SUNXI_CCU_GATE_HWS(bus_hstimer_clk, "bus-hstimer", psi_ahb_hws, 0x73c, BIT(0), 0); static SUNXI_CCU_GATE_DATA(avs_clk, "avs", osc24M, 0x740, BIT(31), 0); static SUNXI_CCU_GATE_HWS(bus_dbg_clk, "bus-dbg", psi_ahb_hws, 0x78c, BIT(0), 0); static SUNXI_CCU_GATE_HWS(bus_pwm_clk, "bus-pwm", apb0_hws, 0x7ac, BIT(0), 0); static SUNXI_CCU_GATE_HWS(bus_iommu_clk, "bus-iommu", apb0_hws, 0x7bc, BIT(0), 0); static const struct clk_hw *dram_parents[] = …; static SUNXI_CCU_MP_HW_WITH_MUX_GATE(dram_clk, "dram", dram_parents, 0x800, 0, 2, /* M */ 8, 2, /* P */ 24, 2, /* mux */ BIT(31), CLK_IS_CRITICAL); static CLK_FIXED_FACTOR_HW(mbus_clk, "mbus", &dram_clk.common.hw, 4, 1, 0); static const struct clk_hw *mbus_hws[] = …; static SUNXI_CCU_GATE_HWS(mbus_dma_clk, "mbus-dma", mbus_hws, 0x804, BIT(0), 0); static SUNXI_CCU_GATE_HWS(mbus_ve_clk, "mbus-ve", mbus_hws, 0x804, BIT(1), 0); static SUNXI_CCU_GATE_HWS(mbus_ce_clk, "mbus-ce", mbus_hws, 0x804, BIT(2), 0); static SUNXI_CCU_GATE_HWS(mbus_tvin_clk, "mbus-tvin", mbus_hws, 0x804, BIT(7), 0); static SUNXI_CCU_GATE_HWS(mbus_csi_clk, "mbus-csi", mbus_hws, 0x804, BIT(8), 0); static SUNXI_CCU_GATE_HWS(mbus_g2d_clk, "mbus-g2d", mbus_hws, 0x804, BIT(10), 0); static SUNXI_CCU_GATE_HWS(mbus_riscv_clk, "mbus-riscv", mbus_hws, 0x804, BIT(11), 0); static SUNXI_CCU_GATE_HWS(bus_dram_clk, "bus-dram", psi_ahb_hws, 0x80c, BIT(0), CLK_IS_CRITICAL); static const struct clk_parent_data mmc0_mmc1_parents[] = …; static SUNXI_CCU_MP_DATA_WITH_MUX_GATE(mmc0_clk, "mmc0", mmc0_mmc1_parents, 0x830, 0, 4, /* M */ 8, 2, /* P */ 24, 3, /* mux */ BIT(31), /* gate */ 0); static SUNXI_CCU_MP_DATA_WITH_MUX_GATE(mmc1_clk, "mmc1", mmc0_mmc1_parents, 0x834, 0, 4, /* M */ 8, 2, /* P */ 24, 3, /* mux */ BIT(31), /* gate */ 0); static const struct clk_parent_data mmc2_parents[] = …; static SUNXI_CCU_MP_DATA_WITH_MUX_GATE(mmc2_clk, "mmc2", mmc2_parents, 0x838, 0, 4, /* M */ 8, 2, /* P */ 24, 3, /* mux */ BIT(31), /* gate */ 0); static SUNXI_CCU_GATE_HWS(bus_mmc0_clk, "bus-mmc0", psi_ahb_hws, 0x84c, BIT(0), 0); static SUNXI_CCU_GATE_HWS(bus_mmc1_clk, "bus-mmc1", psi_ahb_hws, 0x84c, BIT(1), 0); static SUNXI_CCU_GATE_HWS(bus_mmc2_clk, "bus-mmc2", psi_ahb_hws, 0x84c, BIT(2), 0); static SUNXI_CCU_GATE_HWS(bus_uart0_clk, "bus-uart0", apb1_hws, 0x90c, BIT(0), 0); static SUNXI_CCU_GATE_HWS(bus_uart1_clk, "bus-uart1", apb1_hws, 0x90c, BIT(1), 0); static SUNXI_CCU_GATE_HWS(bus_uart2_clk, "bus-uart2", apb1_hws, 0x90c, BIT(2), 0); static SUNXI_CCU_GATE_HWS(bus_uart3_clk, "bus-uart3", apb1_hws, 0x90c, BIT(3), 0); static SUNXI_CCU_GATE_HWS(bus_uart4_clk, "bus-uart4", apb1_hws, 0x90c, BIT(4), 0); static SUNXI_CCU_GATE_HWS(bus_uart5_clk, "bus-uart5", apb1_hws, 0x90c, BIT(5), 0); static SUNXI_CCU_GATE_HWS(bus_i2c0_clk, "bus-i2c0", apb1_hws, 0x91c, BIT(0), 0); static SUNXI_CCU_GATE_HWS(bus_i2c1_clk, "bus-i2c1", apb1_hws, 0x91c, BIT(1), 0); static SUNXI_CCU_GATE_HWS(bus_i2c2_clk, "bus-i2c2", apb1_hws, 0x91c, BIT(2), 0); static SUNXI_CCU_GATE_HWS(bus_i2c3_clk, "bus-i2c3", apb1_hws, 0x91c, BIT(3), 0); static SUNXI_CCU_GATE_HWS(bus_can0_clk, "bus-can0", apb1_hws, 0x92c, BIT(0), 0); static SUNXI_CCU_GATE_HWS(bus_can1_clk, "bus-can1", apb1_hws, 0x92c, BIT(1), 0); static const struct clk_parent_data spi_parents[] = …; static SUNXI_CCU_MP_DATA_WITH_MUX_GATE(spi0_clk, "spi0", spi_parents, 0x940, 0, 4, /* M */ 8, 2, /* P */ 24, 3, /* mux */ BIT(31), /* gate */ 0); static SUNXI_CCU_MP_DATA_WITH_MUX_GATE(spi1_clk, "spi1", spi_parents, 0x944, 0, 4, /* M */ 8, 2, /* P */ 24, 3, /* mux */ BIT(31), /* gate */ 0); static SUNXI_CCU_GATE_HWS(bus_spi0_clk, "bus-spi0", psi_ahb_hws, 0x96c, BIT(0), 0); static SUNXI_CCU_GATE_HWS(bus_spi1_clk, "bus-spi1", psi_ahb_hws, 0x96c, BIT(1), 0); static SUNXI_CCU_GATE_HWS_WITH_PREDIV(emac_25M_clk, "emac-25M", pll_periph0_hws, 0x970, BIT(31) | BIT(30), 24, 0); static SUNXI_CCU_GATE_HWS(bus_emac_clk, "bus-emac", psi_ahb_hws, 0x97c, BIT(0), 0); static const struct clk_parent_data ir_tx_ledc_parents[] = …; static SUNXI_CCU_MP_DATA_WITH_MUX_GATE(ir_tx_clk, "ir-tx", ir_tx_ledc_parents, 0x9c0, 0, 4, /* M */ 8, 2, /* P */ 24, 3, /* mux */ BIT(31), /* gate */ 0); static SUNXI_CCU_GATE_HWS(bus_ir_tx_clk, "bus-ir-tx", apb0_hws, 0x9cc, BIT(0), 0); static SUNXI_CCU_GATE_HWS(bus_gpadc_clk, "bus-gpadc", apb0_hws, 0x9ec, BIT(0), 0); static SUNXI_CCU_GATE_HWS(bus_ths_clk, "bus-ths", apb0_hws, 0x9fc, BIT(0), 0); static const struct clk_hw *i2s_spdif_tx_parents[] = …; static SUNXI_CCU_MP_HW_WITH_MUX_GATE(i2s0_clk, "i2s0", i2s_spdif_tx_parents, 0xa10, 0, 5, /* M */ 8, 2, /* P */ 24, 3, /* mux */ BIT(31), /* gate */ 0); static SUNXI_CCU_MP_HW_WITH_MUX_GATE(i2s1_clk, "i2s1", i2s_spdif_tx_parents, 0xa14, 0, 5, /* M */ 8, 2, /* P */ 24, 3, /* mux */ BIT(31), /* gate */ 0); static SUNXI_CCU_MP_HW_WITH_MUX_GATE(i2s2_clk, "i2s2", i2s_spdif_tx_parents, 0xa18, 0, 5, /* M */ 8, 2, /* P */ 24, 3, /* mux */ BIT(31), /* gate */ 0); static const struct clk_hw *i2s2_asrc_parents[] = …; static SUNXI_CCU_MP_HW_WITH_MUX_GATE(i2s2_asrc_clk, "i2s2-asrc", i2s2_asrc_parents, 0xa1c, 0, 5, /* M */ 8, 2, /* P */ 24, 3, /* mux */ BIT(31), /* gate */ 0); static SUNXI_CCU_GATE_HWS(bus_i2s0_clk, "bus-i2s0", apb0_hws, 0xa20, BIT(0), 0); static SUNXI_CCU_GATE_HWS(bus_i2s1_clk, "bus-i2s1", apb0_hws, 0xa20, BIT(1), 0); static SUNXI_CCU_GATE_HWS(bus_i2s2_clk, "bus-i2s2", apb0_hws, 0xa20, BIT(2), 0); static SUNXI_CCU_MP_HW_WITH_MUX_GATE(spdif_tx_clk, "spdif-tx", i2s_spdif_tx_parents, 0xa24, 0, 5, /* M */ 8, 2, /* P */ 24, 3, /* mux */ BIT(31), /* gate */ 0); static const struct clk_hw *spdif_rx_parents[] = …; static SUNXI_CCU_MP_HW_WITH_MUX_GATE(spdif_rx_clk, "spdif-rx", spdif_rx_parents, 0xa28, 0, 5, /* M */ 8, 2, /* P */ 24, 3, /* mux */ BIT(31), /* gate */ 0); static SUNXI_CCU_GATE_HWS(bus_spdif_clk, "bus-spdif", apb0_hws, 0xa2c, BIT(0), 0); static const struct clk_hw *dmic_codec_parents[] = …; static SUNXI_CCU_MP_HW_WITH_MUX_GATE(dmic_clk, "dmic", dmic_codec_parents, 0xa40, 0, 5, /* M */ 8, 2, /* P */ 24, 3, /* mux */ BIT(31), /* gate */ 0); static SUNXI_CCU_GATE_HWS(bus_dmic_clk, "bus-dmic", apb0_hws, 0xa4c, BIT(0), 0); static SUNXI_CCU_MP_HW_WITH_MUX_GATE(audio_dac_clk, "audio-dac", dmic_codec_parents, 0xa50, 0, 5, /* M */ 8, 2, /* P */ 24, 3, /* mux */ BIT(31), /* gate */ 0); static SUNXI_CCU_MP_HW_WITH_MUX_GATE(audio_adc_clk, "audio-adc", dmic_codec_parents, 0xa54, 0, 5, /* M */ 8, 2, /* P */ 24, 3, /* mux */ BIT(31), /* gate */ 0); static SUNXI_CCU_GATE_HWS(bus_audio_clk, "bus-audio", apb0_hws, 0xa5c, BIT(0), 0); /* * The first parent is a 48 MHz input clock divided by 4. That 48 MHz clock is * a 2x multiplier from osc24M synchronized by pll-periph0, and is also used by * the OHCI module. */ static const struct clk_parent_data usb_ohci_parents[] = …; static const struct ccu_mux_fixed_prediv usb_ohci_predivs[] = …; static struct ccu_mux usb_ohci0_clk = …; static struct ccu_mux usb_ohci1_clk = …; static SUNXI_CCU_GATE_HWS(bus_ohci0_clk, "bus-ohci0", psi_ahb_hws, 0xa8c, BIT(0), 0); static SUNXI_CCU_GATE_HWS(bus_ohci1_clk, "bus-ohci1", psi_ahb_hws, 0xa8c, BIT(1), 0); static SUNXI_CCU_GATE_HWS(bus_ehci0_clk, "bus-ehci0", psi_ahb_hws, 0xa8c, BIT(4), 0); static SUNXI_CCU_GATE_HWS(bus_ehci1_clk, "bus-ehci1", psi_ahb_hws, 0xa8c, BIT(5), 0); static SUNXI_CCU_GATE_HWS(bus_otg_clk, "bus-otg", psi_ahb_hws, 0xa8c, BIT(8), 0); static SUNXI_CCU_GATE_HWS(bus_lradc_clk, "bus-lradc", apb0_hws, 0xa9c, BIT(0), 0); static SUNXI_CCU_GATE_HWS(bus_dpss_top_clk, "bus-dpss-top", psi_ahb_hws, 0xabc, BIT(0), 0); static SUNXI_CCU_GATE_DATA(hdmi_24M_clk, "hdmi-24M", osc24M, 0xb04, BIT(31), 0); static SUNXI_CCU_GATE_HWS_WITH_PREDIV(hdmi_cec_32k_clk, "hdmi-cec-32k", pll_periph0_2x_hws, 0xb10, BIT(30), 36621, 0); static const struct clk_parent_data hdmi_cec_parents[] = …; static SUNXI_CCU_MUX_DATA_WITH_GATE(hdmi_cec_clk, "hdmi-cec", hdmi_cec_parents, 0xb10, 24, 1, /* mux */ BIT(31), /* gate */ 0); static SUNXI_CCU_GATE_HWS(bus_hdmi_clk, "bus-hdmi", psi_ahb_hws, 0xb1c, BIT(0), 0); static const struct clk_parent_data mipi_dsi_parents[] = …; static SUNXI_CCU_M_DATA_WITH_MUX_GATE(mipi_dsi_clk, "mipi-dsi", mipi_dsi_parents, 0xb24, 0, 4, /* M */ 24, 3, /* mux */ BIT(31), /* gate */ CLK_SET_RATE_PARENT); static SUNXI_CCU_GATE_HWS(bus_mipi_dsi_clk, "bus-mipi-dsi", psi_ahb_hws, 0xb4c, BIT(0), 0); static const struct clk_hw *tcon_tve_parents[] = …; static SUNXI_CCU_MP_HW_WITH_MUX_GATE(tcon_lcd0_clk, "tcon-lcd0", tcon_tve_parents, 0xb60, 0, 4, /* M */ 8, 2, /* P */ 24, 3, /* mux */ BIT(31), /* gate */ CLK_SET_RATE_PARENT); static SUNXI_CCU_GATE_HWS(bus_tcon_lcd0_clk, "bus-tcon-lcd0", psi_ahb_hws, 0xb7c, BIT(0), 0); static SUNXI_CCU_MP_HW_WITH_MUX_GATE(tcon_tv_clk, "tcon-tv", tcon_tve_parents, 0xb80, 0, 4, /* M */ 8, 2, /* P */ 24, 3, /* mux */ BIT(31), /* gate */ CLK_SET_RATE_PARENT); static SUNXI_CCU_GATE_HWS(bus_tcon_tv_clk, "bus-tcon-tv", psi_ahb_hws, 0xb9c, BIT(0), 0); static SUNXI_CCU_MP_HW_WITH_MUX_GATE(tve_clk, "tve", tcon_tve_parents, 0xbb0, 0, 4, /* M */ 8, 2, /* P */ 24, 3, /* mux */ BIT(31), /* gate */ 0); static SUNXI_CCU_GATE_HWS(bus_tve_top_clk, "bus-tve-top", psi_ahb_hws, 0xbbc, BIT(0), 0); static SUNXI_CCU_GATE_HWS(bus_tve_clk, "bus-tve", psi_ahb_hws, 0xbbc, BIT(1), 0); static const struct clk_parent_data tvd_parents[] = …; static SUNXI_CCU_M_DATA_WITH_MUX_GATE(tvd_clk, "tvd", tvd_parents, 0xbc0, 0, 5, /* M */ 24, 3, /* mux */ BIT(31), /* gate */ 0); static SUNXI_CCU_GATE_HWS(bus_tvd_top_clk, "bus-tvd-top", psi_ahb_hws, 0xbdc, BIT(0), 0); static SUNXI_CCU_GATE_HWS(bus_tvd_clk, "bus-tvd", psi_ahb_hws, 0xbdc, BIT(1), 0); static SUNXI_CCU_MP_DATA_WITH_MUX_GATE(ledc_clk, "ledc", ir_tx_ledc_parents, 0xbf0, 0, 4, /* M */ 8, 2, /* P */ 24, 1, /* mux */ BIT(31), /* gate */ 0); static SUNXI_CCU_GATE_HWS(bus_ledc_clk, "bus-ledc", psi_ahb_hws, 0xbfc, BIT(0), 0); static const struct clk_hw *csi_top_parents[] = …; static SUNXI_CCU_M_HW_WITH_MUX_GATE(csi_top_clk, "csi-top", csi_top_parents, 0xc04, 0, 4, /* M */ 24, 3, /* mux */ BIT(31), /* gate */ 0); static const struct clk_parent_data csi_mclk_parents[] = …; static SUNXI_CCU_M_DATA_WITH_MUX_GATE(csi_mclk_clk, "csi-mclk", csi_mclk_parents, 0xc08, 0, 5, /* M */ 24, 3, /* mux */ BIT(31), /* gate */ 0); static SUNXI_CCU_GATE_HWS(bus_csi_clk, "bus-csi", psi_ahb_hws, 0xc1c, BIT(0), 0); static const struct clk_parent_data tpadc_parents[] = …; static SUNXI_CCU_MUX_DATA_WITH_GATE(tpadc_clk, "tpadc", tpadc_parents, 0xc50, 24, 3, /* mux */ BIT(31), /* gate */ 0); static SUNXI_CCU_GATE_HWS(bus_tpadc_clk, "bus-tpadc", apb0_hws, 0xc5c, BIT(0), 0); static SUNXI_CCU_GATE_HWS(bus_tzma_clk, "bus-tzma", apb0_hws, 0xc6c, BIT(0), 0); static const struct clk_parent_data dsp_parents[] = …; static SUNXI_CCU_M_DATA_WITH_MUX_GATE(dsp_clk, "dsp", dsp_parents, 0xc70, 0, 5, /* M */ 24, 3, /* mux */ BIT(31), /* gate */ 0); static SUNXI_CCU_GATE_HWS(bus_dsp_cfg_clk, "bus-dsp-cfg", psi_ahb_hws, 0xc7c, BIT(1), 0); /* * The RISC-V gate is not modelled - it is in a separate register (0xd04) * and has a special key field. The clock is critical anyway. */ static const struct clk_parent_data riscv_parents[] = …; static SUNXI_CCU_M_DATA_WITH_MUX(riscv_clk, "riscv", riscv_parents, 0xd00, 0, 5, /* M */ 24, 3, /* mux */ CLK_SET_RATE_PARENT | CLK_IS_CRITICAL); /* The riscv-axi clk must be divided by at least 2. */ static struct clk_div_table riscv_axi_table[] = …; static SUNXI_CCU_DIV_TABLE_HW(riscv_axi_clk, "riscv-axi", &riscv_clk.common.hw, 0xd00, 8, 2, riscv_axi_table, 0); static SUNXI_CCU_GATE_HWS(bus_riscv_cfg_clk, "bus-riscv-cfg", psi_ahb_hws, 0xd0c, BIT(0), CLK_IS_CRITICAL); static SUNXI_CCU_GATE_DATA(fanout_24M_clk, "fanout-24M", osc24M, 0xf30, BIT(0), 0); static SUNXI_CCU_GATE_DATA_WITH_PREDIV(fanout_12M_clk, "fanout-12M", osc24M, 0xf30, BIT(1), 2, 0); static SUNXI_CCU_GATE_HWS_WITH_PREDIV(fanout_16M_clk, "fanout-16M", pll_periph0_2x_hws, 0xf30, BIT(2), 75, 0); static SUNXI_CCU_GATE_HWS_WITH_PREDIV(fanout_25M_clk, "fanout-25M", pll_periph0_hws, 0xf30, BIT(3), 24, 0); static SUNXI_CCU_GATE_HWS_WITH_PREDIV(fanout_32k_clk, "fanout-32k", pll_periph0_2x_hws, 0xf30, BIT(4), 36621, 0); /* This clock has a second divider that is not modelled and forced to 0. */ #define SUN20I_D1_FANOUT_27M_REG … static const struct clk_hw *fanout_27M_parents[] = …; static SUNXI_CCU_M_HW_WITH_MUX_GATE(fanout_27M_clk, "fanout-27M", fanout_27M_parents, 0xf34, 0, 5, /* M */ 24, 2, /* mux */ BIT(31), /* gate */ 0); static SUNXI_CCU_M_HWS_WITH_GATE(fanout_pclk_clk, "fanout-pclk", apb0_hws, 0xf38, 0, 5, /* M */ BIT(31), /* gate */ 0); static const struct clk_hw *fanout_parents[] = …; static SUNXI_CCU_MUX_HW_WITH_GATE(fanout0_clk, "fanout0", fanout_parents, 0xf3c, 0, 3, /* mux */ BIT(21), /* gate */ 0); static SUNXI_CCU_MUX_HW_WITH_GATE(fanout1_clk, "fanout1", fanout_parents, 0xf3c, 3, 3, /* mux */ BIT(22), /* gate */ 0); static SUNXI_CCU_MUX_HW_WITH_GATE(fanout2_clk, "fanout2", fanout_parents, 0xf3c, 6, 3, /* mux */ BIT(23), /* gate */ 0); static struct ccu_common *sun20i_d1_ccu_clks[] = …; static struct clk_hw_onecell_data sun20i_d1_hw_clks = …; static struct ccu_reset_map sun20i_d1_ccu_resets[] = …; static const struct sunxi_ccu_desc sun20i_d1_ccu_desc = …; static const u32 pll_regs[] = …; static const u32 pll_video_regs[] = …; static struct ccu_mux_nb sun20i_d1_riscv_nb = …; static int sun20i_d1_ccu_probe(struct platform_device *pdev) { … } static const struct of_device_id sun20i_d1_ccu_ids[] = …; MODULE_DEVICE_TABLE(of, sun20i_d1_ccu_ids); static struct platform_driver sun20i_d1_ccu_driver = …; module_platform_driver(…) …; MODULE_IMPORT_NS(…); MODULE_DESCRIPTION(…) …; MODULE_LICENSE(…) …;
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