/* SPDX-License-Identifier: GPL-2.0-or-later */ /* * Copyright 2016 Chen-Yu Tsai * * Chen-Yu Tsai <[email protected]> */ #ifndef _CCU_SUN6I_A31_H_ #define _CCU_SUN6I_A31_H_ #include <dt-bindings/clock/sun6i-a31-ccu.h> #include <dt-bindings/reset/sun6i-a31-ccu.h> #define CLK_PLL_CPU … #define CLK_PLL_AUDIO_BASE … #define CLK_PLL_AUDIO … #define CLK_PLL_AUDIO_2X … #define CLK_PLL_AUDIO_4X … #define CLK_PLL_AUDIO_8X … #define CLK_PLL_VIDEO0 … /* The PLL_VIDEO0_2X clock is exported */ #define CLK_PLL_VE … #define CLK_PLL_DDR … /* The PLL_PERIPH clock is exported */ #define CLK_PLL_PERIPH_2X … #define CLK_PLL_VIDEO1 … /* The PLL_VIDEO1_2X clock is exported */ #define CLK_PLL_GPU … /* The PLL_VIDEO1_2X clock is exported */ #define CLK_PLL9 … #define CLK_PLL10 … /* The CPUX clock is exported */ #define CLK_AXI … #define CLK_AHB1 … #define CLK_APB1 … #define CLK_APB2 … /* All the bus gates are exported */ /* The first bunch of module clocks are exported */ /* EMAC clock is not implemented */ #define CLK_MDFS … #define CLK_SDRAM0 … #define CLK_SDRAM1 … /* All the DRAM gates are exported */ /* Some more module clocks are exported */ #define CLK_MBUS0 … #define CLK_MBUS1 … /* Some more module clocks and external clock outputs are exported */ #define CLK_NUMBER … #endif /* _CCU_SUN6I_A31_H_ */
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