/* SPDX-License-Identifier: GPL-2.0-or-later */ /* * Copyright 2016 Maxime Ripard * * Maxime Ripard <[email protected]> */ #ifndef _CCU_SUN8I_A23_A33_H_ #define _CCU_SUN8I_A23_A33_H_ #include <dt-bindings/clock/sun8i-a23-a33-ccu.h> #include <dt-bindings/reset/sun8i-a23-a33-ccu.h> #define CLK_PLL_CPUX … #define CLK_PLL_AUDIO_BASE … #define CLK_PLL_AUDIO … #define CLK_PLL_AUDIO_2X … #define CLK_PLL_AUDIO_4X … #define CLK_PLL_AUDIO_8X … #define CLK_PLL_VIDEO … #define CLK_PLL_VIDEO_2X … #define CLK_PLL_VE … #define CLK_PLL_DDR0 … #define CLK_PLL_PERIPH … #define CLK_PLL_PERIPH_2X … #define CLK_PLL_GPU … /* The PLL MIPI clock is exported */ #define CLK_PLL_HSIC … #define CLK_PLL_DE … #define CLK_PLL_DDR1 … #define CLK_PLL_DDR … /* The CPUX clock is exported */ #define CLK_AXI … #define CLK_AHB1 … #define CLK_APB1 … #define CLK_APB2 … /* All the bus gates are exported */ /* The first part of the mod clocks is exported */ #define CLK_DRAM … /* Some more module clocks are exported */ #define CLK_MBUS … /* And the last module clocks are exported */ #define CLK_NUMBER … #endif /* _CCU_SUN8I_A23_A33_H_ */
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