// SPDX-License-Identifier: GPL-2.0-only /* * Copyright (c) 2016 Chen-Yu Tsai * * Chen-Yu Tsai <[email protected]> * * Based on ccu-sun8i-h3.c by Maxime Ripard. */ #include <linux/clk-provider.h> #include <linux/io.h> #include <linux/module.h> #include <linux/platform_device.h> #include "ccu_common.h" #include "ccu_reset.h" #include "ccu_div.h" #include "ccu_gate.h" #include "ccu_mp.h" #include "ccu_mult.h" #include "ccu_mux.h" #include "ccu_nk.h" #include "ccu_nkm.h" #include "ccu_nkmp.h" #include "ccu_nm.h" #include "ccu_phase.h" #include "ccu_sdm.h" #include "ccu-sun6i-a31.h" static SUNXI_CCU_NKM_WITH_GATE_LOCK(pll_cpu_clk, "pll-cpu", "osc24M", 0x000, 8, 5, /* N */ 4, 2, /* K */ 0, 2, /* M */ BIT(31), /* gate */ BIT(28), /* lock */ 0); /* * The Audio PLL is supposed to have 4 outputs: 3 fixed factors from * the base (2x, 4x and 8x), and one variable divider (the one true * pll audio). * * With sigma-delta modulation for fractional-N on the audio PLL, * we have to use specific dividers. This means the variable divider * can no longer be used, as the audio codec requests the exact clock * rates we support through this mechanism. So we now hard code the * variable divider to 1. This means the clock rates will no longer * match the clock names. */ #define SUN6I_A31_PLL_AUDIO_REG … static struct ccu_sdm_setting pll_audio_sdm_table[] = …; static SUNXI_CCU_NM_WITH_SDM_GATE_LOCK(pll_audio_base_clk, "pll-audio-base", "osc24M", 0x008, 8, 7, /* N */ 0, 5, /* M */ pll_audio_sdm_table, BIT(24), 0x284, BIT(31), BIT(31), /* gate */ BIT(28), /* lock */ CLK_SET_RATE_UNGATE); static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_video0_clk, "pll-video0", "osc24M", 0x010, 8, 7, /* N */ 0, 4, /* M */ BIT(24), /* frac enable */ BIT(25), /* frac select */ 270000000, /* frac rate 0 */ 297000000, /* frac rate 1 */ BIT(31), /* gate */ BIT(28), /* lock */ CLK_SET_RATE_UNGATE); static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_ve_clk, "pll-ve", "osc24M", 0x018, 8, 7, /* N */ 0, 4, /* M */ BIT(24), /* frac enable */ BIT(25), /* frac select */ 270000000, /* frac rate 0 */ 297000000, /* frac rate 1 */ BIT(31), /* gate */ BIT(28), /* lock */ CLK_SET_RATE_UNGATE); static SUNXI_CCU_NKM_WITH_GATE_LOCK(pll_ddr_clk, "pll-ddr", "osc24M", 0x020, 8, 5, /* N */ 4, 2, /* K */ 0, 2, /* M */ BIT(31), /* gate */ BIT(28), /* lock */ CLK_SET_RATE_UNGATE); static SUNXI_CCU_NK_WITH_GATE_LOCK_POSTDIV(pll_periph_clk, "pll-periph", "osc24M", 0x028, 8, 5, /* N */ 4, 2, /* K */ BIT(31), /* gate */ BIT(28), /* lock */ 2, /* post-div */ CLK_SET_RATE_UNGATE); static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_video1_clk, "pll-video1", "osc24M", 0x030, 8, 7, /* N */ 0, 4, /* M */ BIT(24), /* frac enable */ BIT(25), /* frac select */ 270000000, /* frac rate 0 */ 297000000, /* frac rate 1 */ BIT(31), /* gate */ BIT(28), /* lock */ CLK_SET_RATE_UNGATE); static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_gpu_clk, "pll-gpu", "osc24M", 0x038, 8, 7, /* N */ 0, 4, /* M */ BIT(24), /* frac enable */ BIT(25), /* frac select */ 270000000, /* frac rate 0 */ 297000000, /* frac rate 1 */ BIT(31), /* gate */ BIT(28), /* lock */ CLK_SET_RATE_UNGATE); /* * The MIPI PLL has 2 modes: "MIPI" and "HDMI". * * The MIPI mode is a standard NKM-style clock. The HDMI mode is an * integer / fractional clock with switchable multipliers and dividers. * This is not supported here. We hardcode the PLL to MIPI mode. */ #define SUN6I_A31_PLL_MIPI_REG … static const char * const pll_mipi_parents[] = …; static SUNXI_CCU_NKM_WITH_MUX_GATE_LOCK(pll_mipi_clk, "pll-mipi", pll_mipi_parents, 0x040, 8, 4, /* N */ 4, 2, /* K */ 0, 4, /* M */ 21, 0, /* mux */ BIT(31) | BIT(23) | BIT(22), /* gate */ BIT(28), /* lock */ CLK_SET_RATE_UNGATE); static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll9_clk, "pll9", "osc24M", 0x044, 8, 7, /* N */ 0, 4, /* M */ BIT(24), /* frac enable */ BIT(25), /* frac select */ 270000000, /* frac rate 0 */ 297000000, /* frac rate 1 */ BIT(31), /* gate */ BIT(28), /* lock */ CLK_SET_RATE_UNGATE); static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll10_clk, "pll10", "osc24M", 0x048, 8, 7, /* N */ 0, 4, /* M */ BIT(24), /* frac enable */ BIT(25), /* frac select */ 270000000, /* frac rate 0 */ 297000000, /* frac rate 1 */ BIT(31), /* gate */ BIT(28), /* lock */ CLK_SET_RATE_UNGATE); static const char * const cpux_parents[] = …; static SUNXI_CCU_MUX(cpu_clk, "cpu", cpux_parents, 0x050, 16, 2, CLK_SET_RATE_PARENT | CLK_IS_CRITICAL); static struct clk_div_table axi_div_table[] = …; static SUNXI_CCU_DIV_TABLE(axi_clk, "axi", "cpu", 0x050, 0, 3, axi_div_table, 0); #define SUN6I_A31_AHB1_REG … static const char * const ahb1_parents[] = …; static const struct ccu_mux_var_prediv ahb1_predivs[] = …; static struct ccu_div ahb1_clk = …; static struct clk_div_table apb1_div_table[] = …; static SUNXI_CCU_DIV_TABLE(apb1_clk, "apb1", "ahb1", 0x054, 8, 2, apb1_div_table, 0); static const char * const apb2_parents[] = …; static SUNXI_CCU_MP_WITH_MUX(apb2_clk, "apb2", apb2_parents, 0x058, 0, 5, /* M */ 16, 2, /* P */ 24, 2, /* mux */ 0); static SUNXI_CCU_GATE(ahb1_mipidsi_clk, "ahb1-mipidsi", "ahb1", 0x060, BIT(1), 0); static SUNXI_CCU_GATE(ahb1_ss_clk, "ahb1-ss", "ahb1", 0x060, BIT(5), 0); static SUNXI_CCU_GATE(ahb1_dma_clk, "ahb1-dma", "ahb1", 0x060, BIT(6), 0); static SUNXI_CCU_GATE(ahb1_mmc0_clk, "ahb1-mmc0", "ahb1", 0x060, BIT(8), 0); static SUNXI_CCU_GATE(ahb1_mmc1_clk, "ahb1-mmc1", "ahb1", 0x060, BIT(9), 0); static SUNXI_CCU_GATE(ahb1_mmc2_clk, "ahb1-mmc2", "ahb1", 0x060, BIT(10), 0); static SUNXI_CCU_GATE(ahb1_mmc3_clk, "ahb1-mmc3", "ahb1", 0x060, BIT(11), 0); static SUNXI_CCU_GATE(ahb1_nand1_clk, "ahb1-nand1", "ahb1", 0x060, BIT(12), 0); static SUNXI_CCU_GATE(ahb1_nand0_clk, "ahb1-nand0", "ahb1", 0x060, BIT(13), 0); static SUNXI_CCU_GATE(ahb1_sdram_clk, "ahb1-sdram", "ahb1", 0x060, BIT(14), 0); static SUNXI_CCU_GATE(ahb1_emac_clk, "ahb1-emac", "ahb1", 0x060, BIT(17), 0); static SUNXI_CCU_GATE(ahb1_ts_clk, "ahb1-ts", "ahb1", 0x060, BIT(18), 0); static SUNXI_CCU_GATE(ahb1_hstimer_clk, "ahb1-hstimer", "ahb1", 0x060, BIT(19), 0); static SUNXI_CCU_GATE(ahb1_spi0_clk, "ahb1-spi0", "ahb1", 0x060, BIT(20), 0); static SUNXI_CCU_GATE(ahb1_spi1_clk, "ahb1-spi1", "ahb1", 0x060, BIT(21), 0); static SUNXI_CCU_GATE(ahb1_spi2_clk, "ahb1-spi2", "ahb1", 0x060, BIT(22), 0); static SUNXI_CCU_GATE(ahb1_spi3_clk, "ahb1-spi3", "ahb1", 0x060, BIT(23), 0); static SUNXI_CCU_GATE(ahb1_otg_clk, "ahb1-otg", "ahb1", 0x060, BIT(24), 0); static SUNXI_CCU_GATE(ahb1_ehci0_clk, "ahb1-ehci0", "ahb1", 0x060, BIT(26), 0); static SUNXI_CCU_GATE(ahb1_ehci1_clk, "ahb1-ehci1", "ahb1", 0x060, BIT(27), 0); static SUNXI_CCU_GATE(ahb1_ohci0_clk, "ahb1-ohci0", "ahb1", 0x060, BIT(29), 0); static SUNXI_CCU_GATE(ahb1_ohci1_clk, "ahb1-ohci1", "ahb1", 0x060, BIT(30), 0); static SUNXI_CCU_GATE(ahb1_ohci2_clk, "ahb1-ohci2", "ahb1", 0x060, BIT(31), 0); static SUNXI_CCU_GATE(ahb1_ve_clk, "ahb1-ve", "ahb1", 0x064, BIT(0), 0); static SUNXI_CCU_GATE(ahb1_lcd0_clk, "ahb1-lcd0", "ahb1", 0x064, BIT(4), 0); static SUNXI_CCU_GATE(ahb1_lcd1_clk, "ahb1-lcd1", "ahb1", 0x064, BIT(5), 0); static SUNXI_CCU_GATE(ahb1_csi_clk, "ahb1-csi", "ahb1", 0x064, BIT(8), 0); static SUNXI_CCU_GATE(ahb1_hdmi_clk, "ahb1-hdmi", "ahb1", 0x064, BIT(11), 0); static SUNXI_CCU_GATE(ahb1_be0_clk, "ahb1-be0", "ahb1", 0x064, BIT(12), 0); static SUNXI_CCU_GATE(ahb1_be1_clk, "ahb1-be1", "ahb1", 0x064, BIT(13), 0); static SUNXI_CCU_GATE(ahb1_fe0_clk, "ahb1-fe0", "ahb1", 0x064, BIT(14), 0); static SUNXI_CCU_GATE(ahb1_fe1_clk, "ahb1-fe1", "ahb1", 0x064, BIT(15), 0); static SUNXI_CCU_GATE(ahb1_mp_clk, "ahb1-mp", "ahb1", 0x064, BIT(18), 0); static SUNXI_CCU_GATE(ahb1_gpu_clk, "ahb1-gpu", "ahb1", 0x064, BIT(20), 0); static SUNXI_CCU_GATE(ahb1_deu0_clk, "ahb1-deu0", "ahb1", 0x064, BIT(23), 0); static SUNXI_CCU_GATE(ahb1_deu1_clk, "ahb1-deu1", "ahb1", 0x064, BIT(24), 0); static SUNXI_CCU_GATE(ahb1_drc0_clk, "ahb1-drc0", "ahb1", 0x064, BIT(25), 0); static SUNXI_CCU_GATE(ahb1_drc1_clk, "ahb1-drc1", "ahb1", 0x064, BIT(26), 0); static SUNXI_CCU_GATE(apb1_codec_clk, "apb1-codec", "apb1", 0x068, BIT(0), 0); static SUNXI_CCU_GATE(apb1_spdif_clk, "apb1-spdif", "apb1", 0x068, BIT(1), 0); static SUNXI_CCU_GATE(apb1_digital_mic_clk, "apb1-digital-mic", "apb1", 0x068, BIT(4), 0); static SUNXI_CCU_GATE(apb1_pio_clk, "apb1-pio", "apb1", 0x068, BIT(5), 0); static SUNXI_CCU_GATE(apb1_daudio0_clk, "apb1-daudio0", "apb1", 0x068, BIT(12), 0); static SUNXI_CCU_GATE(apb1_daudio1_clk, "apb1-daudio1", "apb1", 0x068, BIT(13), 0); static SUNXI_CCU_GATE(apb2_i2c0_clk, "apb2-i2c0", "apb2", 0x06c, BIT(0), 0); static SUNXI_CCU_GATE(apb2_i2c1_clk, "apb2-i2c1", "apb2", 0x06c, BIT(1), 0); static SUNXI_CCU_GATE(apb2_i2c2_clk, "apb2-i2c2", "apb2", 0x06c, BIT(2), 0); static SUNXI_CCU_GATE(apb2_i2c3_clk, "apb2-i2c3", "apb2", 0x06c, BIT(3), 0); static SUNXI_CCU_GATE(apb2_uart0_clk, "apb2-uart0", "apb2", 0x06c, BIT(16), 0); static SUNXI_CCU_GATE(apb2_uart1_clk, "apb2-uart1", "apb2", 0x06c, BIT(17), 0); static SUNXI_CCU_GATE(apb2_uart2_clk, "apb2-uart2", "apb2", 0x06c, BIT(18), 0); static SUNXI_CCU_GATE(apb2_uart3_clk, "apb2-uart3", "apb2", 0x06c, BIT(19), 0); static SUNXI_CCU_GATE(apb2_uart4_clk, "apb2-uart4", "apb2", 0x06c, BIT(20), 0); static SUNXI_CCU_GATE(apb2_uart5_clk, "apb2-uart5", "apb2", 0x06c, BIT(21), 0); static const char * const mod0_default_parents[] = …; static SUNXI_CCU_MP_WITH_MUX_GATE(nand0_clk, "nand0", mod0_default_parents, 0x080, 0, 4, /* M */ 16, 2, /* P */ 24, 2, /* mux */ BIT(31), /* gate */ 0); static SUNXI_CCU_MP_WITH_MUX_GATE(nand1_clk, "nand1", mod0_default_parents, 0x084, 0, 4, /* M */ 16, 2, /* P */ 24, 2, /* mux */ BIT(31), /* gate */ 0); static SUNXI_CCU_MP_WITH_MUX_GATE(mmc0_clk, "mmc0", mod0_default_parents, 0x088, 0, 4, /* M */ 16, 2, /* P */ 24, 2, /* mux */ BIT(31), /* gate */ 0); static SUNXI_CCU_PHASE(mmc0_sample_clk, "mmc0_sample", "mmc0", 0x088, 20, 3, 0); static SUNXI_CCU_PHASE(mmc0_output_clk, "mmc0_output", "mmc0", 0x088, 8, 3, 0); static SUNXI_CCU_MP_WITH_MUX_GATE(mmc1_clk, "mmc1", mod0_default_parents, 0x08c, 0, 4, /* M */ 16, 2, /* P */ 24, 2, /* mux */ BIT(31), /* gate */ 0); static SUNXI_CCU_PHASE(mmc1_sample_clk, "mmc1_sample", "mmc1", 0x08c, 20, 3, 0); static SUNXI_CCU_PHASE(mmc1_output_clk, "mmc1_output", "mmc1", 0x08c, 8, 3, 0); static SUNXI_CCU_MP_WITH_MUX_GATE(mmc2_clk, "mmc2", mod0_default_parents, 0x090, 0, 4, /* M */ 16, 2, /* P */ 24, 2, /* mux */ BIT(31), /* gate */ 0); static SUNXI_CCU_PHASE(mmc2_sample_clk, "mmc2_sample", "mmc2", 0x090, 20, 3, 0); static SUNXI_CCU_PHASE(mmc2_output_clk, "mmc2_output", "mmc2", 0x090, 8, 3, 0); static SUNXI_CCU_MP_WITH_MUX_GATE(mmc3_clk, "mmc3", mod0_default_parents, 0x094, 0, 4, /* M */ 16, 2, /* P */ 24, 2, /* mux */ BIT(31), /* gate */ 0); static SUNXI_CCU_PHASE(mmc3_sample_clk, "mmc3_sample", "mmc3", 0x094, 20, 3, 0); static SUNXI_CCU_PHASE(mmc3_output_clk, "mmc3_output", "mmc3", 0x094, 8, 3, 0); static SUNXI_CCU_MP_WITH_MUX_GATE(ts_clk, "ts", mod0_default_parents, 0x098, 0, 4, /* M */ 16, 2, /* P */ 24, 2, /* mux */ BIT(31), /* gate */ 0); static SUNXI_CCU_MP_WITH_MUX_GATE(ss_clk, "ss", mod0_default_parents, 0x09c, 0, 4, /* M */ 16, 2, /* P */ 24, 2, /* mux */ BIT(31), /* gate */ 0); static SUNXI_CCU_MP_WITH_MUX_GATE(spi0_clk, "spi0", mod0_default_parents, 0x0a0, 0, 4, /* M */ 16, 2, /* P */ 24, 2, /* mux */ BIT(31), /* gate */ 0); static SUNXI_CCU_MP_WITH_MUX_GATE(spi1_clk, "spi1", mod0_default_parents, 0x0a4, 0, 4, /* M */ 16, 2, /* P */ 24, 2, /* mux */ BIT(31), /* gate */ 0); static SUNXI_CCU_MP_WITH_MUX_GATE(spi2_clk, "spi2", mod0_default_parents, 0x0a8, 0, 4, /* M */ 16, 2, /* P */ 24, 2, /* mux */ BIT(31), /* gate */ 0); static SUNXI_CCU_MP_WITH_MUX_GATE(spi3_clk, "spi3", mod0_default_parents, 0x0ac, 0, 4, /* M */ 16, 2, /* P */ 24, 2, /* mux */ BIT(31), /* gate */ 0); static const char * const daudio_parents[] = …; static SUNXI_CCU_MUX_WITH_GATE(daudio0_clk, "daudio0", daudio_parents, 0x0b0, 16, 2, BIT(31), CLK_SET_RATE_PARENT); static SUNXI_CCU_MUX_WITH_GATE(daudio1_clk, "daudio1", daudio_parents, 0x0b4, 16, 2, BIT(31), CLK_SET_RATE_PARENT); static SUNXI_CCU_MUX_WITH_GATE(spdif_clk, "spdif", daudio_parents, 0x0c0, 16, 2, BIT(31), CLK_SET_RATE_PARENT); static SUNXI_CCU_GATE(usb_phy0_clk, "usb-phy0", "osc24M", 0x0cc, BIT(8), 0); static SUNXI_CCU_GATE(usb_phy1_clk, "usb-phy1", "osc24M", 0x0cc, BIT(9), 0); static SUNXI_CCU_GATE(usb_phy2_clk, "usb-phy2", "osc24M", 0x0cc, BIT(10), 0); static SUNXI_CCU_GATE(usb_ohci0_clk, "usb-ohci0", "osc24M", 0x0cc, BIT(16), 0); static SUNXI_CCU_GATE(usb_ohci1_clk, "usb-ohci1", "osc24M", 0x0cc, BIT(17), 0); static SUNXI_CCU_GATE(usb_ohci2_clk, "usb-ohci2", "osc24M", 0x0cc, BIT(18), 0); /* TODO emac clk not supported yet */ static const char * const dram_parents[] = …; static SUNXI_CCU_MP_WITH_MUX_GATE(mdfs_clk, "mdfs", dram_parents, 0x0f0, 0, 4, /* M */ 16, 2, /* P */ 24, 2, /* mux */ BIT(31), /* gate */ CLK_IS_CRITICAL); static SUNXI_CCU_M_WITH_MUX(sdram0_clk, "sdram0", dram_parents, 0x0f4, 0, 4, 4, 1, CLK_IS_CRITICAL); static SUNXI_CCU_M_WITH_MUX(sdram1_clk, "sdram1", dram_parents, 0x0f4, 8, 4, 12, 1, CLK_IS_CRITICAL); static SUNXI_CCU_GATE(dram_ve_clk, "dram-ve", "mdfs", 0x100, BIT(0), 0); static SUNXI_CCU_GATE(dram_csi_isp_clk, "dram-csi-isp", "mdfs", 0x100, BIT(1), 0); static SUNXI_CCU_GATE(dram_ts_clk, "dram-ts", "mdfs", 0x100, BIT(3), 0); static SUNXI_CCU_GATE(dram_drc0_clk, "dram-drc0", "mdfs", 0x100, BIT(16), 0); static SUNXI_CCU_GATE(dram_drc1_clk, "dram-drc1", "mdfs", 0x100, BIT(17), 0); static SUNXI_CCU_GATE(dram_deu0_clk, "dram-deu0", "mdfs", 0x100, BIT(18), 0); static SUNXI_CCU_GATE(dram_deu1_clk, "dram-deu1", "mdfs", 0x100, BIT(19), 0); static SUNXI_CCU_GATE(dram_fe0_clk, "dram-fe0", "mdfs", 0x100, BIT(24), 0); static SUNXI_CCU_GATE(dram_fe1_clk, "dram-fe1", "mdfs", 0x100, BIT(25), 0); static SUNXI_CCU_GATE(dram_be0_clk, "dram-be0", "mdfs", 0x100, BIT(26), 0); static SUNXI_CCU_GATE(dram_be1_clk, "dram-be1", "mdfs", 0x100, BIT(27), 0); static SUNXI_CCU_GATE(dram_mp_clk, "dram-mp", "mdfs", 0x100, BIT(28), 0); static const char * const de_parents[] = …; static SUNXI_CCU_M_WITH_MUX_GATE(be0_clk, "be0", de_parents, 0x104, 0, 4, 24, 3, BIT(31), 0); static SUNXI_CCU_M_WITH_MUX_GATE(be1_clk, "be1", de_parents, 0x108, 0, 4, 24, 3, BIT(31), 0); static SUNXI_CCU_M_WITH_MUX_GATE(fe0_clk, "fe0", de_parents, 0x10c, 0, 4, 24, 3, BIT(31), 0); static SUNXI_CCU_M_WITH_MUX_GATE(fe1_clk, "fe1", de_parents, 0x110, 0, 4, 24, 3, BIT(31), 0); static const char * const mp_parents[] = …; static SUNXI_CCU_M_WITH_MUX_GATE(mp_clk, "mp", mp_parents, 0x114, 0, 4, 24, 3, BIT(31), 0); static const char * const lcd_ch0_parents[] = …; static SUNXI_CCU_MUX_WITH_GATE(lcd0_ch0_clk, "lcd0-ch0", lcd_ch0_parents, 0x118, 24, 2, BIT(31), CLK_SET_RATE_PARENT); static SUNXI_CCU_MUX_WITH_GATE(lcd1_ch0_clk, "lcd1-ch0", lcd_ch0_parents, 0x11c, 24, 2, BIT(31), CLK_SET_RATE_PARENT); static const char * const lcd_ch1_parents[] = …; static SUNXI_CCU_M_WITH_MUX_GATE(lcd0_ch1_clk, "lcd0-ch1", lcd_ch1_parents, 0x12c, 0, 4, 24, 3, BIT(31), CLK_SET_RATE_PARENT); static SUNXI_CCU_M_WITH_MUX_GATE(lcd1_ch1_clk, "lcd1-ch1", lcd_ch1_parents, 0x130, 0, 4, 24, 3, BIT(31), CLK_SET_RATE_PARENT); static const char * const csi_sclk_parents[] = …; static SUNXI_CCU_M_WITH_MUX_GATE(csi0_sclk_clk, "csi0-sclk", csi_sclk_parents, 0x134, 16, 4, 24, 3, BIT(31), 0); static const char * const csi_mclk_parents[] = …; static const u8 csi_mclk_table[] = …; static struct ccu_div csi0_mclk_clk = …; static struct ccu_div csi1_mclk_clk = …; static SUNXI_CCU_M_WITH_GATE(ve_clk, "ve", "pll-ve", 0x13c, 16, 3, BIT(31), 0); static SUNXI_CCU_GATE(codec_clk, "codec", "pll-audio", 0x140, BIT(31), CLK_SET_RATE_PARENT); static SUNXI_CCU_GATE(avs_clk, "avs", "osc24M", 0x144, BIT(31), 0); static SUNXI_CCU_GATE(digital_mic_clk, "digital-mic", "pll-audio", 0x148, BIT(31), CLK_SET_RATE_PARENT); static SUNXI_CCU_M_WITH_MUX_GATE(hdmi_clk, "hdmi", lcd_ch1_parents, 0x150, 0, 4, 24, 2, BIT(31), CLK_SET_RATE_PARENT); static SUNXI_CCU_GATE(hdmi_ddc_clk, "ddc", "osc24M", 0x150, BIT(30), 0); static SUNXI_CCU_GATE(ps_clk, "ps", "lcd1-ch1", 0x140, BIT(31), 0); static const char * const mbus_parents[] = …; static SUNXI_CCU_MP_WITH_MUX_GATE(mbus0_clk, "mbus0", mbus_parents, 0x15c, 0, 3, /* M */ 16, 2, /* P */ 24, 2, /* mux */ BIT(31), /* gate */ CLK_IS_CRITICAL); static SUNXI_CCU_MP_WITH_MUX_GATE(mbus1_clk, "mbus1", mbus_parents, 0x160, 0, 3, /* M */ 16, 2, /* P */ 24, 2, /* mux */ BIT(31), /* gate */ CLK_IS_CRITICAL); static SUNXI_CCU_M_WITH_MUX_GATE(mipi_dsi_clk, "mipi-dsi", lcd_ch1_parents, 0x168, 16, 3, 24, 2, BIT(31), CLK_SET_RATE_PARENT); static SUNXI_CCU_M_WITH_MUX_GATE(mipi_dsi_dphy_clk, "mipi-dsi-dphy", lcd_ch1_parents, 0x168, 0, 3, 8, 2, BIT(15), CLK_SET_RATE_PARENT); static SUNXI_CCU_M_WITH_MUX_GATE(mipi_csi_dphy_clk, "mipi-csi-dphy", lcd_ch1_parents, 0x16c, 0, 3, 8, 2, BIT(15), 0); static SUNXI_CCU_M_WITH_MUX_GATE(iep_drc0_clk, "iep-drc0", de_parents, 0x180, 0, 3, 24, 2, BIT(31), 0); static SUNXI_CCU_M_WITH_MUX_GATE(iep_drc1_clk, "iep-drc1", de_parents, 0x184, 0, 3, 24, 2, BIT(31), 0); static SUNXI_CCU_M_WITH_MUX_GATE(iep_deu0_clk, "iep-deu0", de_parents, 0x188, 0, 3, 24, 2, BIT(31), 0); static SUNXI_CCU_M_WITH_MUX_GATE(iep_deu1_clk, "iep-deu1", de_parents, 0x18c, 0, 3, 24, 2, BIT(31), 0); static const char * const gpu_parents[] = …; static const struct ccu_mux_fixed_prediv gpu_predivs[] = …; static struct ccu_div gpu_core_clk = …; static struct ccu_div gpu_memory_clk = …; static struct ccu_div gpu_hyd_clk = …; static SUNXI_CCU_M_WITH_MUX_GATE(ats_clk, "ats", mod0_default_parents, 0x1b0, 0, 3, /* M */ 24, 2, /* mux */ BIT(31), /* gate */ 0); static SUNXI_CCU_M_WITH_MUX_GATE(trace_clk, "trace", mod0_default_parents, 0x1b0, 0, 3, /* M */ 24, 2, /* mux */ BIT(31), /* gate */ 0); static const char * const clk_out_parents[] = …; static const u8 clk_out_table[] = …; static const struct ccu_mux_fixed_prediv clk_out_predivs[] = …; static struct ccu_mp out_a_clk = …; static struct ccu_mp out_b_clk = …; static struct ccu_mp out_c_clk = …; static struct ccu_common *sun6i_a31_ccu_clks[] = …; static const struct clk_hw *clk_parent_pll_audio[] = …; /* We hardcode the divider to 1 for now */ static CLK_FIXED_FACTOR_HWS(pll_audio_clk, "pll-audio", clk_parent_pll_audio, 1, 1, CLK_SET_RATE_PARENT); static CLK_FIXED_FACTOR_HWS(pll_audio_2x_clk, "pll-audio-2x", clk_parent_pll_audio, 2, 1, CLK_SET_RATE_PARENT); static CLK_FIXED_FACTOR_HWS(pll_audio_4x_clk, "pll-audio-4x", clk_parent_pll_audio, 1, 1, CLK_SET_RATE_PARENT); static CLK_FIXED_FACTOR_HWS(pll_audio_8x_clk, "pll-audio-8x", clk_parent_pll_audio, 1, 2, CLK_SET_RATE_PARENT); static CLK_FIXED_FACTOR_HW(pll_periph_2x_clk, "pll-periph-2x", &pll_periph_clk.common.hw, 1, 2, 0); static CLK_FIXED_FACTOR_HW(pll_video0_2x_clk, "pll-video0-2x", &pll_video0_clk.common.hw, 1, 2, CLK_SET_RATE_PARENT); static CLK_FIXED_FACTOR_HW(pll_video1_2x_clk, "pll-video1-2x", &pll_video1_clk.common.hw, 1, 2, CLK_SET_RATE_PARENT); static struct clk_hw_onecell_data sun6i_a31_hw_clks = …; static struct ccu_reset_map sun6i_a31_ccu_resets[] = …; static const struct sunxi_ccu_desc sun6i_a31_ccu_desc = …; static struct ccu_mux_nb sun6i_a31_cpu_nb = …; static int sun6i_a31_ccu_probe(struct platform_device *pdev) { … } static const struct of_device_id sun6i_a31_ccu_ids[] = …; MODULE_DEVICE_TABLE(of, sun6i_a31_ccu_ids); static struct platform_driver sun6i_a31_ccu_driver = …; module_platform_driver(…) …; MODULE_IMPORT_NS(…); MODULE_DESCRIPTION(…) …; MODULE_LICENSE(…) …;
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