/* SPDX-License-Identifier: GPL-2.0-or-later */ /* * Copyright 2016 Chen-Yu Tsai * * Chen-Yu Tsai <[email protected]> */ #ifndef _CCU_SUN8I_A83T_H_ #define _CCU_SUN8I_A83T_H_ #include <dt-bindings/clock/sun8i-a83t-ccu.h> #include <dt-bindings/reset/sun8i-a83t-ccu.h> #define CLK_PLL_C0CPUX … #define CLK_PLL_C1CPUX … #define CLK_PLL_AUDIO … #define CLK_PLL_VIDEO0 … #define CLK_PLL_VE … #define CLK_PLL_DDR … /* pll-periph is exported to the PRCM block */ #define CLK_PLL_GPU … #define CLK_PLL_HSIC … /* pll-de is exported for the display engine */ #define CLK_PLL_VIDEO1 … /* The CPUX clocks are exported */ #define CLK_AXI0 … #define CLK_AXI1 … #define CLK_AHB1 … #define CLK_AHB2 … #define CLK_APB1 … #define CLK_APB2 … /* bus gates exported */ #define CLK_CCI400 … /* module and usb clocks exported */ #define CLK_DRAM … /* dram gates and more module clocks exported */ #define CLK_MBUS … /* more module clocks exported */ #define CLK_NUMBER … #endif /* _CCU_SUN8I_A83T_H_ */
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