/* SPDX-License-Identifier: GPL-2.0-or-later */ /* * Copyright (c) 2016 Icenowy Zheng <[email protected]> * * Based on ccu-sun8i-h3.h, which is: * Copyright (c) 2016 Maxime Ripard <[email protected]> */ #ifndef _CCU_SUN8I_V3S_H_ #define _CCU_SUN8I_V3S_H_ #include <dt-bindings/clock/sun8i-v3s-ccu.h> #include <dt-bindings/reset/sun8i-v3s-ccu.h> #define CLK_PLL_CPU … #define CLK_PLL_AUDIO_BASE … #define CLK_PLL_AUDIO … #define CLK_PLL_AUDIO_2X … #define CLK_PLL_AUDIO_4X … #define CLK_PLL_AUDIO_8X … #define CLK_PLL_VIDEO … #define CLK_PLL_VE … #define CLK_PLL_DDR0 … #define CLK_PLL_PERIPH0 … #define CLK_PLL_PERIPH0_2X … #define CLK_PLL_ISP … #define CLK_PLL_PERIPH1 … /* Reserve one number for not implemented and not used PLL_DDR1 */ /* The CPU clock is exported */ #define CLK_AXI … #define CLK_AHB1 … #define CLK_APB1 … #define CLK_APB2 … #define CLK_AHB2 … /* All the bus gates are exported */ /* The first bunch of module clocks are exported */ #define CLK_DRAM … /* All the DRAM gates are exported */ /* Some more module clocks are exported */ #define CLK_MBUS … /* And the GPU module clock is exported */ #define CLK_PLL_DDR1 … #endif /* _CCU_SUN8I_V3S_H_ */
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