// SPDX-License-Identifier: GPL-2.0-only /* * Copyright (c) 2017 Chen-Yu Tsai. All rights reserved. */ #include <linux/clk-provider.h> #include <linux/io.h> #include <linux/module.h> #include <linux/platform_device.h> #include "ccu_common.h" #include "ccu_reset.h" #include "ccu_div.h" #include "ccu_gate.h" #include "ccu_mp.h" #include "ccu_mux.h" #include "ccu_nkmp.h" #include "ccu_nm.h" #include "ccu_phase.h" #include "ccu-sun8i-a83t.h" #define CCU_SUN8I_A83T_LOCK_REG … /* * The CPU PLLs are actually NP clocks, with P being /1 or /4. However * P should only be used for output frequencies lower than 228 MHz. * Neither mainline Linux, U-boot, nor the vendor BSPs use these. * * For now we can just model it as a multiplier clock, and force P to /1. */ #define SUN8I_A83T_PLL_C0CPUX_REG … #define SUN8I_A83T_PLL_C1CPUX_REG … static struct ccu_mult pll_c0cpux_clk = …; static struct ccu_mult pll_c1cpux_clk = …; /* * The Audio PLL has d1, d2 dividers in addition to the usual N, M * factors. Since we only need 2 frequencies from this PLL: 22.5792 MHz * and 24.576 MHz, ignore them for now. Enforce the default for them, * which is d1 = 0, d2 = 1. */ #define SUN8I_A83T_PLL_AUDIO_REG … /* clock rates doubled for post divider */ static struct ccu_sdm_setting pll_audio_sdm_table[] = …; static struct ccu_nm pll_audio_clk = …; /* Some PLLs are input * N / div1 / P. Model them as NKMP with no K */ static struct ccu_nkmp pll_video0_clk = …; static struct ccu_nkmp pll_ve_clk = …; static struct ccu_nkmp pll_ddr_clk = …; static struct ccu_nkmp pll_periph_clk = …; static struct ccu_nkmp pll_gpu_clk = …; static struct ccu_nkmp pll_hsic_clk = …; static struct ccu_nkmp pll_de_clk = …; static struct ccu_nkmp pll_video1_clk = …; static const char * const c0cpux_parents[] = …; static SUNXI_CCU_MUX(c0cpux_clk, "c0cpux", c0cpux_parents, 0x50, 12, 1, CLK_SET_RATE_PARENT | CLK_IS_CRITICAL); static const char * const c1cpux_parents[] = …; static SUNXI_CCU_MUX(c1cpux_clk, "c1cpux", c1cpux_parents, 0x50, 28, 1, CLK_SET_RATE_PARENT | CLK_IS_CRITICAL); static SUNXI_CCU_M(axi0_clk, "axi0", "c0cpux", 0x050, 0, 2, 0); static SUNXI_CCU_M(axi1_clk, "axi1", "c1cpux", 0x050, 16, 2, 0); static const char * const ahb1_parents[] = …; static const struct ccu_mux_var_prediv ahb1_predivs[] = …; static struct ccu_div ahb1_clk = …; static SUNXI_CCU_M(apb1_clk, "apb1", "ahb1", 0x054, 8, 2, 0); static const char * const apb2_parents[] = …; static SUNXI_CCU_MP_WITH_MUX(apb2_clk, "apb2", apb2_parents, 0x058, 0, 5, /* M */ 16, 2, /* P */ 24, 2, /* mux */ 0); static const char * const ahb2_parents[] = …; static const struct ccu_mux_fixed_prediv ahb2_prediv = …; static struct ccu_mux ahb2_clk = …; static SUNXI_CCU_GATE(bus_mipi_dsi_clk, "bus-mipi-dsi", "ahb1", 0x060, BIT(1), 0); static SUNXI_CCU_GATE(bus_ss_clk, "bus-ss", "ahb1", 0x060, BIT(5), 0); static SUNXI_CCU_GATE(bus_dma_clk, "bus-dma", "ahb1", 0x060, BIT(6), 0); static SUNXI_CCU_GATE(bus_mmc0_clk, "bus-mmc0", "ahb1", 0x060, BIT(8), 0); static SUNXI_CCU_GATE(bus_mmc1_clk, "bus-mmc1", "ahb1", 0x060, BIT(9), 0); static SUNXI_CCU_GATE(bus_mmc2_clk, "bus-mmc2", "ahb1", 0x060, BIT(10), 0); static SUNXI_CCU_GATE(bus_nand_clk, "bus-nand", "ahb1", 0x060, BIT(13), 0); static SUNXI_CCU_GATE(bus_dram_clk, "bus-dram", "ahb1", 0x060, BIT(14), 0); static SUNXI_CCU_GATE(bus_emac_clk, "bus-emac", "ahb2", 0x060, BIT(17), 0); static SUNXI_CCU_GATE(bus_hstimer_clk, "bus-hstimer", "ahb1", 0x060, BIT(19), 0); static SUNXI_CCU_GATE(bus_spi0_clk, "bus-spi0", "ahb1", 0x060, BIT(20), 0); static SUNXI_CCU_GATE(bus_spi1_clk, "bus-spi1", "ahb1", 0x060, BIT(21), 0); static SUNXI_CCU_GATE(bus_otg_clk, "bus-otg", "ahb1", 0x060, BIT(24), 0); static SUNXI_CCU_GATE(bus_ehci0_clk, "bus-ehci0", "ahb2", 0x060, BIT(26), 0); static SUNXI_CCU_GATE(bus_ehci1_clk, "bus-ehci1", "ahb2", 0x060, BIT(27), 0); static SUNXI_CCU_GATE(bus_ohci0_clk, "bus-ohci0", "ahb2", 0x060, BIT(29), 0); static SUNXI_CCU_GATE(bus_ve_clk, "bus-ve", "ahb1", 0x064, BIT(0), 0); static SUNXI_CCU_GATE(bus_tcon0_clk, "bus-tcon0", "ahb1", 0x064, BIT(4), 0); static SUNXI_CCU_GATE(bus_tcon1_clk, "bus-tcon1", "ahb1", 0x064, BIT(5), 0); static SUNXI_CCU_GATE(bus_csi_clk, "bus-csi", "ahb1", 0x064, BIT(8), 0); static SUNXI_CCU_GATE(bus_hdmi_clk, "bus-hdmi", "ahb1", 0x064, BIT(11), 0); static SUNXI_CCU_GATE(bus_de_clk, "bus-de", "ahb1", 0x064, BIT(12), 0); static SUNXI_CCU_GATE(bus_gpu_clk, "bus-gpu", "ahb1", 0x064, BIT(20), 0); static SUNXI_CCU_GATE(bus_msgbox_clk, "bus-msgbox", "ahb1", 0x064, BIT(21), 0); static SUNXI_CCU_GATE(bus_spinlock_clk, "bus-spinlock", "ahb1", 0x064, BIT(22), 0); static SUNXI_CCU_GATE(bus_spdif_clk, "bus-spdif", "apb1", 0x068, BIT(1), 0); static SUNXI_CCU_GATE(bus_pio_clk, "bus-pio", "apb1", 0x068, BIT(5), 0); static SUNXI_CCU_GATE(bus_i2s0_clk, "bus-i2s0", "apb1", 0x068, BIT(12), 0); static SUNXI_CCU_GATE(bus_i2s1_clk, "bus-i2s1", "apb1", 0x068, BIT(13), 0); static SUNXI_CCU_GATE(bus_i2s2_clk, "bus-i2s2", "apb1", 0x068, BIT(14), 0); static SUNXI_CCU_GATE(bus_tdm_clk, "bus-tdm", "apb1", 0x068, BIT(15), 0); static SUNXI_CCU_GATE(bus_i2c0_clk, "bus-i2c0", "apb2", 0x06c, BIT(0), 0); static SUNXI_CCU_GATE(bus_i2c1_clk, "bus-i2c1", "apb2", 0x06c, BIT(1), 0); static SUNXI_CCU_GATE(bus_i2c2_clk, "bus-i2c2", "apb2", 0x06c, BIT(2), 0); static SUNXI_CCU_GATE(bus_uart0_clk, "bus-uart0", "apb2", 0x06c, BIT(16), 0); static SUNXI_CCU_GATE(bus_uart1_clk, "bus-uart1", "apb2", 0x06c, BIT(17), 0); static SUNXI_CCU_GATE(bus_uart2_clk, "bus-uart2", "apb2", 0x06c, BIT(18), 0); static SUNXI_CCU_GATE(bus_uart3_clk, "bus-uart3", "apb2", 0x06c, BIT(19), 0); static SUNXI_CCU_GATE(bus_uart4_clk, "bus-uart4", "apb2", 0x06c, BIT(20), 0); static const char * const cci400_parents[] = …; static struct ccu_div cci400_clk = …; static const char * const mod0_default_parents[] = …; static SUNXI_CCU_MP_WITH_MUX_GATE(nand_clk, "nand", mod0_default_parents, 0x080, 0, 4, /* M */ 16, 2, /* P */ 24, 2, /* mux */ BIT(31), /* gate */ 0); static SUNXI_CCU_MP_WITH_MUX_GATE(mmc0_clk, "mmc0", mod0_default_parents, 0x088, 0, 4, /* M */ 16, 2, /* P */ 24, 2, /* mux */ BIT(31), /* gate */ 0); static SUNXI_CCU_PHASE(mmc0_sample_clk, "mmc0-sample", "mmc0", 0x088, 20, 3, 0); static SUNXI_CCU_PHASE(mmc0_output_clk, "mmc0-output", "mmc0", 0x088, 8, 3, 0); static SUNXI_CCU_MP_WITH_MUX_GATE(mmc1_clk, "mmc1", mod0_default_parents, 0x08c, 0, 4, /* M */ 16, 2, /* P */ 24, 2, /* mux */ BIT(31), /* gate */ 0); static SUNXI_CCU_PHASE(mmc1_sample_clk, "mmc1-sample", "mmc1", 0x08c, 20, 3, 0); static SUNXI_CCU_PHASE(mmc1_output_clk, "mmc1-output", "mmc1", 0x08c, 8, 3, 0); static SUNXI_CCU_MP_MMC_WITH_MUX_GATE(mmc2_clk, "mmc2", mod0_default_parents, 0x090, 0); static SUNXI_CCU_PHASE(mmc2_sample_clk, "mmc2-sample", "mmc2", 0x090, 20, 3, 0); static SUNXI_CCU_PHASE(mmc2_output_clk, "mmc2-output", "mmc2", 0x090, 8, 3, 0); static SUNXI_CCU_MP_WITH_MUX_GATE(ss_clk, "ss", mod0_default_parents, 0x09c, 0, 4, /* M */ 16, 2, /* P */ 24, 2, /* mux */ BIT(31), /* gate */ 0); static SUNXI_CCU_MP_WITH_MUX_GATE(spi0_clk, "spi0", mod0_default_parents, 0x0a0, 0, 4, /* M */ 16, 2, /* P */ 24, 4, /* mux */ BIT(31), /* gate */ 0); static SUNXI_CCU_MP_WITH_MUX_GATE(spi1_clk, "spi1", mod0_default_parents, 0x0a4, 0, 4, /* M */ 16, 2, /* P */ 24, 4, /* mux */ BIT(31), /* gate */ 0); static SUNXI_CCU_M_WITH_GATE(i2s0_clk, "i2s0", "pll-audio", 0x0b0, 0, 4, BIT(31), CLK_SET_RATE_PARENT); static SUNXI_CCU_M_WITH_GATE(i2s1_clk, "i2s1", "pll-audio", 0x0b4, 0, 4, BIT(31), CLK_SET_RATE_PARENT); static SUNXI_CCU_M_WITH_GATE(i2s2_clk, "i2s2", "pll-audio", 0x0b8, 0, 4, BIT(31), CLK_SET_RATE_PARENT); static SUNXI_CCU_M_WITH_GATE(tdm_clk, "tdm", "pll-audio", 0x0bc, 0, 4, BIT(31), CLK_SET_RATE_PARENT); static SUNXI_CCU_M_WITH_GATE(spdif_clk, "spdif", "pll-audio", 0x0c0, 0, 4, BIT(31), CLK_SET_RATE_PARENT); static SUNXI_CCU_GATE(usb_phy0_clk, "usb-phy0", "osc24M", 0x0cc, BIT(8), 0); static SUNXI_CCU_GATE(usb_phy1_clk, "usb-phy1", "osc24M", 0x0cc, BIT(9), 0); static SUNXI_CCU_GATE(usb_hsic_clk, "usb-hsic", "pll-hsic", 0x0cc, BIT(10), 0); static struct ccu_gate usb_hsic_12m_clk = …; static SUNXI_CCU_GATE(usb_ohci0_clk, "usb-ohci0", "osc24M", 0x0cc, BIT(16), 0); /* TODO divider has minimum of 2 */ static SUNXI_CCU_M(dram_clk, "dram", "pll-ddr", 0x0f4, 0, 4, CLK_IS_CRITICAL); static SUNXI_CCU_GATE(dram_ve_clk, "dram-ve", "dram", 0x100, BIT(0), 0); static SUNXI_CCU_GATE(dram_csi_clk, "dram-csi", "dram", 0x100, BIT(1), 0); static const char * const tcon0_parents[] = …; static SUNXI_CCU_MUX_WITH_GATE(tcon0_clk, "tcon0", tcon0_parents, 0x118, 24, 3, BIT(31), CLK_SET_RATE_PARENT); static const char * const tcon1_parents[] = …; static SUNXI_CCU_M_WITH_MUX_GATE(tcon1_clk, "tcon1", tcon1_parents, 0x11c, 0, 4, 24, 2, BIT(31), CLK_SET_RATE_PARENT); static SUNXI_CCU_GATE(csi_misc_clk, "csi-misc", "osc24M", 0x130, BIT(16), 0); static SUNXI_CCU_GATE(mipi_csi_clk, "mipi-csi", "osc24M", 0x130, BIT(31), 0); static const char * const csi_mclk_parents[] = …; static const u8 csi_mclk_table[] = …; static SUNXI_CCU_M_WITH_MUX_TABLE_GATE(csi_mclk_clk, "csi-mclk", csi_mclk_parents, csi_mclk_table, 0x134, 0, 5, /* M */ 8, 3, /* mux */ BIT(15), /* gate */ 0); static const char * const csi_sclk_parents[] = …; static const u8 csi_sclk_table[] = …; static SUNXI_CCU_M_WITH_MUX_TABLE_GATE(csi_sclk_clk, "csi-sclk", csi_sclk_parents, csi_sclk_table, 0x134, 16, 4, /* M */ 24, 3, /* mux */ BIT(31), /* gate */ 0); static SUNXI_CCU_M_WITH_GATE(ve_clk, "ve", "pll-ve", 0x13c, 16, 3, BIT(31), CLK_SET_RATE_PARENT); static SUNXI_CCU_GATE(avs_clk, "avs", "osc24M", 0x144, BIT(31), 0); static const char * const hdmi_parents[] = …; static SUNXI_CCU_M_WITH_MUX_GATE(hdmi_clk, "hdmi", hdmi_parents, 0x150, 0, 4, /* M */ 24, 2, /* mux */ BIT(31), /* gate */ CLK_SET_RATE_PARENT); static SUNXI_CCU_GATE(hdmi_slow_clk, "hdmi-slow", "osc24M", 0x154, BIT(31), 0); static const char * const mbus_parents[] = …; static SUNXI_CCU_M_WITH_MUX_GATE(mbus_clk, "mbus", mbus_parents, 0x15c, 0, 3, /* M */ 24, 2, /* mux */ BIT(31), /* gate */ CLK_IS_CRITICAL); static const char * const mipi_dsi0_parents[] = …; static const u8 mipi_dsi0_table[] = …; static SUNXI_CCU_M_WITH_MUX_TABLE_GATE(mipi_dsi0_clk, "mipi-dsi0", mipi_dsi0_parents, mipi_dsi0_table, 0x168, 0, 4, /* M */ 24, 4, /* mux */ BIT(31), /* gate */ CLK_SET_RATE_PARENT); static const char * const mipi_dsi1_parents[] = …; static const u8 mipi_dsi1_table[] = …; static SUNXI_CCU_M_WITH_MUX_TABLE_GATE(mipi_dsi1_clk, "mipi-dsi1", mipi_dsi1_parents, mipi_dsi1_table, 0x16c, 0, 4, /* M */ 24, 4, /* mux */ BIT(31), /* gate */ CLK_SET_RATE_PARENT); static SUNXI_CCU_M_WITH_GATE(gpu_core_clk, "gpu-core", "pll-gpu", 0x1a0, 0, 3, BIT(31), CLK_SET_RATE_PARENT); static const char * const gpu_memory_parents[] = …; static SUNXI_CCU_M_WITH_MUX_GATE(gpu_memory_clk, "gpu-memory", gpu_memory_parents, 0x1a4, 0, 3, /* M */ 24, 1, /* mux */ BIT(31), /* gate */ CLK_SET_RATE_PARENT); static SUNXI_CCU_M_WITH_GATE(gpu_hyd_clk, "gpu-hyd", "pll-gpu", 0x1a8, 0, 3, BIT(31), CLK_SET_RATE_PARENT); static struct ccu_common *sun8i_a83t_ccu_clks[] = …; static struct clk_hw_onecell_data sun8i_a83t_hw_clks = …; static struct ccu_reset_map sun8i_a83t_ccu_resets[] = …; static const struct sunxi_ccu_desc sun8i_a83t_ccu_desc = …; #define SUN8I_A83T_PLL_P_SHIFT … #define SUN8I_A83T_PLL_N_SHIFT … #define SUN8I_A83T_PLL_N_WIDTH … static void sun8i_a83t_cpu_pll_fixup(void __iomem *reg) { … } static int sun8i_a83t_ccu_probe(struct platform_device *pdev) { … } static const struct of_device_id sun8i_a83t_ccu_ids[] = …; MODULE_DEVICE_TABLE(of, sun8i_a83t_ccu_ids); static struct platform_driver sun8i_a83t_ccu_driver = …; module_platform_driver(…) …; MODULE_IMPORT_NS(…); MODULE_DESCRIPTION(…) …; MODULE_LICENSE(…) …;
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