/* SPDX-License-Identifier: GPL-2.0-or-later */ /* * Copyright 2017 Icenowy Zheng <[email protected]> */ #ifndef _CCU_SUN8I_R40_H_ #define _CCU_SUN8I_R40_H_ #include <dt-bindings/clock/sun8i-r40-ccu.h> #include <dt-bindings/reset/sun8i-r40-ccu.h> #define CLK_OSC_12M … #define CLK_PLL_CPU … #define CLK_PLL_AUDIO_BASE … #define CLK_PLL_AUDIO … #define CLK_PLL_AUDIO_2X … #define CLK_PLL_AUDIO_4X … #define CLK_PLL_AUDIO_8X … /* PLL_VIDEO0 is exported */ #define CLK_PLL_VIDEO0_2X … #define CLK_PLL_VE … #define CLK_PLL_DDR0 … #define CLK_PLL_PERIPH0 … #define CLK_PLL_PERIPH0_SATA … #define CLK_PLL_PERIPH0_2X … #define CLK_PLL_PERIPH1 … #define CLK_PLL_PERIPH1_2X … /* PLL_VIDEO1 is exported */ #define CLK_PLL_VIDEO1_2X … #define CLK_PLL_SATA … #define CLK_PLL_SATA_OUT … #define CLK_PLL_GPU … #define CLK_PLL_MIPI … #define CLK_PLL_DE … #define CLK_PLL_DDR1 … /* The CPU clock is exported */ #define CLK_AXI … #define CLK_AHB1 … #define CLK_APB1 … #define CLK_APB2 … /* All the bus gates are exported */ /* The first bunch of module clocks are exported */ #define CLK_DRAM … /* All the DRAM gates are exported */ /* Some more module clocks are exported */ #define CLK_NUMBER … #endif /* _CCU_SUN8I_R40_H_ */
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