// SPDX-License-Identifier: GPL-2.0-only /* * Copyright (c) 2017 Icenowy Zheng <[email protected]> */ #include <linux/clk-provider.h> #include <linux/io.h> #include <linux/module.h> #include <linux/platform_device.h> #include <linux/regmap.h> #include "ccu_common.h" #include "ccu_reset.h" #include "ccu_div.h" #include "ccu_gate.h" #include "ccu_mp.h" #include "ccu_mult.h" #include "ccu_nk.h" #include "ccu_nkm.h" #include "ccu_nkmp.h" #include "ccu_nm.h" #include "ccu_phase.h" #include "ccu-sun8i-r40.h" /* TODO: The result of N*K is required to be in [10, 88] range. */ static struct ccu_nkmp pll_cpu_clk = …; /* * The Audio PLL is supposed to have 4 outputs: 3 fixed factors from * the base (2x, 4x and 8x), and one variable divider (the one true * pll audio). * * With sigma-delta modulation for fractional-N on the audio PLL, * we have to use specific dividers. This means the variable divider * can no longer be used, as the audio codec requests the exact clock * rates we support through this mechanism. So we now hard code the * variable divider to 1. This means the clock rates will no longer * match the clock names. */ #define SUN8I_R40_PLL_AUDIO_REG … static struct ccu_sdm_setting pll_audio_sdm_table[] = …; static SUNXI_CCU_NM_WITH_SDM_GATE_LOCK(pll_audio_base_clk, "pll-audio-base", "osc24M", 0x008, 8, 7, /* N */ 0, 5, /* M */ pll_audio_sdm_table, BIT(24), 0x284, BIT(31), BIT(31), /* gate */ BIT(28), /* lock */ CLK_SET_RATE_UNGATE); static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK_MIN_MAX(pll_video0_clk, "pll-video0", "osc24M", 0x0010, 192000000, /* Minimum rate */ 1008000000, /* Maximum rate */ 8, 7, /* N */ 0, 4, /* M */ BIT(24), /* frac enable */ BIT(25), /* frac select */ 270000000, /* frac rate 0 */ 297000000, /* frac rate 1 */ BIT(31), /* gate */ BIT(28), /* lock */ CLK_SET_RATE_UNGATE); /* TODO: The result of N/M is required to be in [8, 25] range. */ static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_ve_clk, "pll-ve", "osc24M", 0x0018, 8, 7, /* N */ 0, 4, /* M */ BIT(24), /* frac enable */ BIT(25), /* frac select */ 270000000, /* frac rate 0 */ 297000000, /* frac rate 1 */ BIT(31), /* gate */ BIT(28), /* lock */ CLK_SET_RATE_UNGATE); /* TODO: The result of N*K is required to be in [10, 77] range. */ static SUNXI_CCU_NKM_WITH_GATE_LOCK(pll_ddr0_clk, "pll-ddr0", "osc24M", 0x020, 8, 5, /* N */ 4, 2, /* K */ 0, 2, /* M */ BIT(31), /* gate */ BIT(28), /* lock */ CLK_SET_RATE_UNGATE); /* TODO: The result of N*K is required to be in [21, 58] range. */ static struct ccu_nk pll_periph0_clk = …; static struct ccu_div pll_periph0_sata_clk = …; /* TODO: The result of N*K is required to be in [21, 58] range. */ static struct ccu_nk pll_periph1_clk = …; static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK_MIN_MAX(pll_video1_clk, "pll-video1", "osc24M", 0x030, 192000000, /* Minimum rate */ 1008000000, /* Maximum rate */ 8, 7, /* N */ 0, 4, /* M */ BIT(24), /* frac enable */ BIT(25), /* frac select */ 270000000, /* frac rate 0 */ 297000000, /* frac rate 1 */ BIT(31), /* gate */ BIT(28), /* lock */ CLK_SET_RATE_UNGATE); static struct ccu_nkm pll_sata_clk = …; static const char * const pll_sata_out_parents[] = …; static SUNXI_CCU_MUX_WITH_GATE(pll_sata_out_clk, "pll-sata-out", pll_sata_out_parents, 0x034, 30, 1, /* mux */ BIT(14), /* gate */ CLK_SET_RATE_PARENT); /* TODO: The result of N/M is required to be in [8, 25] range. */ static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_gpu_clk, "pll-gpu", "osc24M", 0x038, 8, 7, /* N */ 0, 4, /* M */ BIT(24), /* frac enable */ BIT(25), /* frac select */ 270000000, /* frac rate 0 */ 297000000, /* frac rate 1 */ BIT(31), /* gate */ BIT(28), /* lock */ CLK_SET_RATE_UNGATE); /* * The MIPI PLL has 2 modes: "MIPI" and "HDMI". * * The MIPI mode is a standard NKM-style clock. The HDMI mode is an * integer / fractional clock with switchable multipliers and dividers. * This is not supported here. We hardcode the PLL to MIPI mode. * * TODO: In the MIPI mode, M/N is required to be equal or lesser than 3, * which cannot be implemented now. */ #define SUN8I_R40_PLL_MIPI_REG … static const char * const pll_mipi_parents[] = …; static struct ccu_nkm pll_mipi_clk = …; /* TODO: The result of N/M is required to be in [8, 25] range. */ static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_de_clk, "pll-de", "osc24M", 0x048, 8, 7, /* N */ 0, 4, /* M */ BIT(24), /* frac enable */ BIT(25), /* frac select */ 270000000, /* frac rate 0 */ 297000000, /* frac rate 1 */ BIT(31), /* gate */ BIT(28), /* lock */ CLK_SET_RATE_UNGATE); /* TODO: The N factor is required to be in [16, 75] range. */ static SUNXI_CCU_NM_WITH_GATE_LOCK(pll_ddr1_clk, "pll-ddr1", "osc24M", 0x04c, 8, 7, /* N */ 0, 2, /* M */ BIT(31), /* gate */ BIT(28), /* lock */ CLK_SET_RATE_UNGATE); static const char * const cpu_parents[] = …; static SUNXI_CCU_MUX(cpu_clk, "cpu", cpu_parents, 0x050, 16, 2, CLK_IS_CRITICAL | CLK_SET_RATE_PARENT); static SUNXI_CCU_M(axi_clk, "axi", "cpu", 0x050, 0, 2, 0); static const char * const ahb1_parents[] = …; static const struct ccu_mux_var_prediv ahb1_predivs[] = …; static struct ccu_div ahb1_clk = …; static struct clk_div_table apb1_div_table[] = …; static SUNXI_CCU_DIV_TABLE(apb1_clk, "apb1", "ahb1", 0x054, 8, 2, apb1_div_table, 0); static const char * const apb2_parents[] = …; static SUNXI_CCU_MP_WITH_MUX(apb2_clk, "apb2", apb2_parents, 0x058, 0, 5, /* M */ 16, 2, /* P */ 24, 2, /* mux */ 0); static SUNXI_CCU_GATE(bus_mipi_dsi_clk, "bus-mipi-dsi", "ahb1", 0x060, BIT(1), 0); static SUNXI_CCU_GATE(bus_ce_clk, "bus-ce", "ahb1", 0x060, BIT(5), 0); static SUNXI_CCU_GATE(bus_dma_clk, "bus-dma", "ahb1", 0x060, BIT(6), 0); static SUNXI_CCU_GATE(bus_mmc0_clk, "bus-mmc0", "ahb1", 0x060, BIT(8), 0); static SUNXI_CCU_GATE(bus_mmc1_clk, "bus-mmc1", "ahb1", 0x060, BIT(9), 0); static SUNXI_CCU_GATE(bus_mmc2_clk, "bus-mmc2", "ahb1", 0x060, BIT(10), 0); static SUNXI_CCU_GATE(bus_mmc3_clk, "bus-mmc3", "ahb1", 0x060, BIT(11), 0); static SUNXI_CCU_GATE(bus_nand_clk, "bus-nand", "ahb1", 0x060, BIT(13), 0); static SUNXI_CCU_GATE(bus_dram_clk, "bus-dram", "ahb1", 0x060, BIT(14), 0); static SUNXI_CCU_GATE(bus_emac_clk, "bus-emac", "ahb1", 0x060, BIT(17), 0); static SUNXI_CCU_GATE(bus_ts_clk, "bus-ts", "ahb1", 0x060, BIT(18), 0); static SUNXI_CCU_GATE(bus_hstimer_clk, "bus-hstimer", "ahb1", 0x060, BIT(19), 0); static SUNXI_CCU_GATE(bus_spi0_clk, "bus-spi0", "ahb1", 0x060, BIT(20), 0); static SUNXI_CCU_GATE(bus_spi1_clk, "bus-spi1", "ahb1", 0x060, BIT(21), 0); static SUNXI_CCU_GATE(bus_spi2_clk, "bus-spi2", "ahb1", 0x060, BIT(22), 0); static SUNXI_CCU_GATE(bus_spi3_clk, "bus-spi3", "ahb1", 0x060, BIT(23), 0); static SUNXI_CCU_GATE(bus_sata_clk, "bus-sata", "ahb1", 0x060, BIT(24), 0); static SUNXI_CCU_GATE(bus_otg_clk, "bus-otg", "ahb1", 0x060, BIT(25), 0); static SUNXI_CCU_GATE(bus_ehci0_clk, "bus-ehci0", "ahb1", 0x060, BIT(26), 0); static SUNXI_CCU_GATE(bus_ehci1_clk, "bus-ehci1", "ahb1", 0x060, BIT(27), 0); static SUNXI_CCU_GATE(bus_ehci2_clk, "bus-ehci2", "ahb1", 0x060, BIT(28), 0); static SUNXI_CCU_GATE(bus_ohci0_clk, "bus-ohci0", "ahb1", 0x060, BIT(29), 0); static SUNXI_CCU_GATE(bus_ohci1_clk, "bus-ohci1", "ahb1", 0x060, BIT(30), 0); static SUNXI_CCU_GATE(bus_ohci2_clk, "bus-ohci2", "ahb1", 0x060, BIT(31), 0); static SUNXI_CCU_GATE(bus_ve_clk, "bus-ve", "ahb1", 0x064, BIT(0), 0); static SUNXI_CCU_GATE(bus_mp_clk, "bus-mp", "ahb1", 0x064, BIT(2), 0); static SUNXI_CCU_GATE(bus_deinterlace_clk, "bus-deinterlace", "ahb1", 0x064, BIT(5), 0); static SUNXI_CCU_GATE(bus_csi0_clk, "bus-csi0", "ahb1", 0x064, BIT(8), 0); static SUNXI_CCU_GATE(bus_csi1_clk, "bus-csi1", "ahb1", 0x064, BIT(9), 0); static SUNXI_CCU_GATE(bus_hdmi0_clk, "bus-hdmi0", "ahb1", 0x064, BIT(10), 0); static SUNXI_CCU_GATE(bus_hdmi1_clk, "bus-hdmi1", "ahb1", 0x064, BIT(11), 0); static SUNXI_CCU_GATE(bus_de_clk, "bus-de", "ahb1", 0x064, BIT(12), 0); static SUNXI_CCU_GATE(bus_tve0_clk, "bus-tve0", "ahb1", 0x064, BIT(13), 0); static SUNXI_CCU_GATE(bus_tve1_clk, "bus-tve1", "ahb1", 0x064, BIT(14), 0); static SUNXI_CCU_GATE(bus_tve_top_clk, "bus-tve-top", "ahb1", 0x064, BIT(15), 0); static SUNXI_CCU_GATE(bus_gmac_clk, "bus-gmac", "ahb1", 0x064, BIT(17), 0); static SUNXI_CCU_GATE(bus_gpu_clk, "bus-gpu", "ahb1", 0x064, BIT(20), 0); static SUNXI_CCU_GATE(bus_tvd0_clk, "bus-tvd0", "ahb1", 0x064, BIT(21), 0); static SUNXI_CCU_GATE(bus_tvd1_clk, "bus-tvd1", "ahb1", 0x064, BIT(22), 0); static SUNXI_CCU_GATE(bus_tvd2_clk, "bus-tvd2", "ahb1", 0x064, BIT(23), 0); static SUNXI_CCU_GATE(bus_tvd3_clk, "bus-tvd3", "ahb1", 0x064, BIT(24), 0); static SUNXI_CCU_GATE(bus_tvd_top_clk, "bus-tvd-top", "ahb1", 0x064, BIT(25), 0); static SUNXI_CCU_GATE(bus_tcon_lcd0_clk, "bus-tcon-lcd0", "ahb1", 0x064, BIT(26), 0); static SUNXI_CCU_GATE(bus_tcon_lcd1_clk, "bus-tcon-lcd1", "ahb1", 0x064, BIT(27), 0); static SUNXI_CCU_GATE(bus_tcon_tv0_clk, "bus-tcon-tv0", "ahb1", 0x064, BIT(28), 0); static SUNXI_CCU_GATE(bus_tcon_tv1_clk, "bus-tcon-tv1", "ahb1", 0x064, BIT(29), 0); static SUNXI_CCU_GATE(bus_tcon_top_clk, "bus-tcon-top", "ahb1", 0x064, BIT(30), 0); static SUNXI_CCU_GATE(bus_codec_clk, "bus-codec", "apb1", 0x068, BIT(0), 0); static SUNXI_CCU_GATE(bus_spdif_clk, "bus-spdif", "apb1", 0x068, BIT(1), 0); static SUNXI_CCU_GATE(bus_ac97_clk, "bus-ac97", "apb1", 0x068, BIT(2), 0); static SUNXI_CCU_GATE(bus_pio_clk, "bus-pio", "apb1", 0x068, BIT(5), 0); static SUNXI_CCU_GATE(bus_ir0_clk, "bus-ir0", "apb1", 0x068, BIT(6), 0); static SUNXI_CCU_GATE(bus_ir1_clk, "bus-ir1", "apb1", 0x068, BIT(7), 0); static SUNXI_CCU_GATE(bus_ths_clk, "bus-ths", "apb1", 0x068, BIT(8), 0); static SUNXI_CCU_GATE(bus_keypad_clk, "bus-keypad", "apb1", 0x068, BIT(10), 0); static SUNXI_CCU_GATE(bus_i2s0_clk, "bus-i2s0", "apb1", 0x068, BIT(12), 0); static SUNXI_CCU_GATE(bus_i2s1_clk, "bus-i2s1", "apb1", 0x068, BIT(13), 0); static SUNXI_CCU_GATE(bus_i2s2_clk, "bus-i2s2", "apb1", 0x068, BIT(14), 0); static SUNXI_CCU_GATE(bus_i2c0_clk, "bus-i2c0", "apb2", 0x06c, BIT(0), 0); static SUNXI_CCU_GATE(bus_i2c1_clk, "bus-i2c1", "apb2", 0x06c, BIT(1), 0); static SUNXI_CCU_GATE(bus_i2c2_clk, "bus-i2c2", "apb2", 0x06c, BIT(2), 0); static SUNXI_CCU_GATE(bus_i2c3_clk, "bus-i2c3", "apb2", 0x06c, BIT(3), 0); /* * In datasheet here's "Reserved", however the gate exists in BSP soucre * code. */ static SUNXI_CCU_GATE(bus_can_clk, "bus-can", "apb2", 0x06c, BIT(4), 0); static SUNXI_CCU_GATE(bus_scr_clk, "bus-scr", "apb2", 0x06c, BIT(5), 0); static SUNXI_CCU_GATE(bus_ps20_clk, "bus-ps20", "apb2", 0x06c, BIT(6), 0); static SUNXI_CCU_GATE(bus_ps21_clk, "bus-ps21", "apb2", 0x06c, BIT(7), 0); static SUNXI_CCU_GATE(bus_i2c4_clk, "bus-i2c4", "apb2", 0x06c, BIT(15), 0); static SUNXI_CCU_GATE(bus_uart0_clk, "bus-uart0", "apb2", 0x06c, BIT(16), 0); static SUNXI_CCU_GATE(bus_uart1_clk, "bus-uart1", "apb2", 0x06c, BIT(17), 0); static SUNXI_CCU_GATE(bus_uart2_clk, "bus-uart2", "apb2", 0x06c, BIT(18), 0); static SUNXI_CCU_GATE(bus_uart3_clk, "bus-uart3", "apb2", 0x06c, BIT(19), 0); static SUNXI_CCU_GATE(bus_uart4_clk, "bus-uart4", "apb2", 0x06c, BIT(20), 0); static SUNXI_CCU_GATE(bus_uart5_clk, "bus-uart5", "apb2", 0x06c, BIT(21), 0); static SUNXI_CCU_GATE(bus_uart6_clk, "bus-uart6", "apb2", 0x06c, BIT(22), 0); static SUNXI_CCU_GATE(bus_uart7_clk, "bus-uart7", "apb2", 0x06c, BIT(23), 0); static SUNXI_CCU_GATE(bus_dbg_clk, "bus-dbg", "ahb1", 0x070, BIT(7), 0); static const char * const ths_parents[] = …; static struct ccu_div ths_clk = …; static const char * const mod0_default_parents[] = …; static SUNXI_CCU_MP_WITH_MUX_GATE(nand_clk, "nand", mod0_default_parents, 0x080, 0, 4, /* M */ 16, 2, /* P */ 24, 2, /* mux */ BIT(31), /* gate */ 0); static SUNXI_CCU_MP_WITH_MUX_GATE(mmc0_clk, "mmc0", mod0_default_parents, 0x088, 0, 4, /* M */ 16, 2, /* P */ 24, 2, /* mux */ BIT(31), /* gate */ 0); static SUNXI_CCU_MP_WITH_MUX_GATE(mmc1_clk, "mmc1", mod0_default_parents, 0x08c, 0, 4, /* M */ 16, 2, /* P */ 24, 2, /* mux */ BIT(31), /* gate */ 0); static SUNXI_CCU_MP_WITH_MUX_GATE(mmc2_clk, "mmc2", mod0_default_parents, 0x090, 0, 4, /* M */ 16, 2, /* P */ 24, 2, /* mux */ BIT(31), /* gate */ 0); static SUNXI_CCU_MP_WITH_MUX_GATE(mmc3_clk, "mmc3", mod0_default_parents, 0x094, 0, 4, /* M */ 16, 2, /* P */ 24, 2, /* mux */ BIT(31), /* gate */ 0); static const char * const ts_parents[] = …; static SUNXI_CCU_MP_WITH_MUX_GATE(ts_clk, "ts", ts_parents, 0x098, 0, 4, /* M */ 16, 2, /* P */ 24, 4, /* mux */ BIT(31), /* gate */ 0); static const char * const ce_parents[] = …; static SUNXI_CCU_MP_WITH_MUX_GATE(ce_clk, "ce", ce_parents, 0x09c, 0, 4, /* M */ 16, 2, /* P */ 24, 2, /* mux */ BIT(31), /* gate */ 0); static SUNXI_CCU_MP_WITH_MUX_GATE(spi0_clk, "spi0", mod0_default_parents, 0x0a0, 0, 4, /* M */ 16, 2, /* P */ 24, 2, /* mux */ BIT(31), /* gate */ 0); static SUNXI_CCU_MP_WITH_MUX_GATE(spi1_clk, "spi1", mod0_default_parents, 0x0a4, 0, 4, /* M */ 16, 2, /* P */ 24, 2, /* mux */ BIT(31), /* gate */ 0); static SUNXI_CCU_MP_WITH_MUX_GATE(spi2_clk, "spi2", mod0_default_parents, 0x0a8, 0, 4, /* M */ 16, 2, /* P */ 24, 2, /* mux */ BIT(31), /* gate */ 0); static SUNXI_CCU_MP_WITH_MUX_GATE(spi3_clk, "spi3", mod0_default_parents, 0x0ac, 0, 4, /* M */ 16, 2, /* P */ 24, 2, /* mux */ BIT(31), /* gate */ 0); static const char * const i2s_parents[] = …; static SUNXI_CCU_MUX_WITH_GATE(i2s0_clk, "i2s0", i2s_parents, 0x0b0, 16, 2, BIT(31), CLK_SET_RATE_PARENT); static SUNXI_CCU_MUX_WITH_GATE(i2s1_clk, "i2s1", i2s_parents, 0x0b4, 16, 2, BIT(31), CLK_SET_RATE_PARENT); static SUNXI_CCU_MUX_WITH_GATE(i2s2_clk, "i2s2", i2s_parents, 0x0b8, 16, 2, BIT(31), CLK_SET_RATE_PARENT); static SUNXI_CCU_MUX_WITH_GATE(ac97_clk, "ac97", i2s_parents, 0x0bc, 16, 2, BIT(31), CLK_SET_RATE_PARENT); static SUNXI_CCU_MUX_WITH_GATE(spdif_clk, "spdif", i2s_parents, 0x0c0, 16, 2, BIT(31), CLK_SET_RATE_PARENT); static const char * const keypad_parents[] = …; static const u8 keypad_table[] = …; static struct ccu_mp keypad_clk = …; static const char * const sata_parents[] = …; static SUNXI_CCU_MUX_WITH_GATE(sata_clk, "sata", sata_parents, 0x0c8, 24, 1, BIT(31), CLK_SET_RATE_PARENT); /* * There are 3 OHCI 12M clock source selection bits in this register. * We will force them to 0 (12M divided from 48M). */ #define SUN8I_R40_USB_CLK_REG … static SUNXI_CCU_GATE(usb_phy0_clk, "usb-phy0", "osc24M", 0x0cc, BIT(8), 0); static SUNXI_CCU_GATE(usb_phy1_clk, "usb-phy1", "osc24M", 0x0cc, BIT(9), 0); static SUNXI_CCU_GATE(usb_phy2_clk, "usb-phy2", "osc24M", 0x0cc, BIT(10), 0); static SUNXI_CCU_GATE(usb_ohci0_clk, "usb-ohci0", "osc12M", 0x0cc, BIT(16), 0); static SUNXI_CCU_GATE(usb_ohci1_clk, "usb-ohci1", "osc12M", 0x0cc, BIT(17), 0); static SUNXI_CCU_GATE(usb_ohci2_clk, "usb-ohci2", "osc12M", 0x0cc, BIT(18), 0); static const char * const ir_parents[] = …; static SUNXI_CCU_MP_WITH_MUX_GATE(ir0_clk, "ir0", ir_parents, 0x0d0, 0, 4, /* M */ 16, 2, /* P */ 24, 2, /* mux */ BIT(31), /* gate */ 0); static SUNXI_CCU_MP_WITH_MUX_GATE(ir1_clk, "ir1", ir_parents, 0x0d4, 0, 4, /* M */ 16, 2, /* P */ 24, 2, /* mux */ BIT(31), /* gate */ 0); static const char * const dram_parents[] = …; static SUNXI_CCU_M_WITH_MUX(dram_clk, "dram", dram_parents, 0x0f4, 0, 2, 20, 2, CLK_IS_CRITICAL); static SUNXI_CCU_GATE(dram_ve_clk, "dram-ve", "dram", 0x100, BIT(0), 0); static SUNXI_CCU_GATE(dram_csi0_clk, "dram-csi0", "dram", 0x100, BIT(1), 0); static SUNXI_CCU_GATE(dram_csi1_clk, "dram-csi1", "dram", 0x100, BIT(2), 0); static SUNXI_CCU_GATE(dram_ts_clk, "dram-ts", "dram", 0x100, BIT(3), 0); static SUNXI_CCU_GATE(dram_tvd_clk, "dram-tvd", "dram", 0x100, BIT(4), 0); static SUNXI_CCU_GATE(dram_mp_clk, "dram-mp", "dram", 0x100, BIT(5), 0); static SUNXI_CCU_GATE(dram_deinterlace_clk, "dram-deinterlace", "dram", 0x100, BIT(6), 0); static const char * const de_parents[] = …; static SUNXI_CCU_M_WITH_MUX_GATE(de_clk, "de", de_parents, 0x104, 0, 4, 24, 3, BIT(31), CLK_SET_RATE_PARENT); static SUNXI_CCU_M_WITH_MUX_GATE(mp_clk, "mp", de_parents, 0x108, 0, 4, 24, 3, BIT(31), 0); static const char * const tcon_parents[] = …; static SUNXI_CCU_MUX_WITH_GATE(tcon_lcd0_clk, "tcon-lcd0", tcon_parents, 0x110, 24, 3, BIT(31), CLK_SET_RATE_PARENT); static SUNXI_CCU_MUX_WITH_GATE(tcon_lcd1_clk, "tcon-lcd1", tcon_parents, 0x114, 24, 3, BIT(31), CLK_SET_RATE_PARENT); static SUNXI_CCU_M_WITH_MUX_GATE(tcon_tv0_clk, "tcon-tv0", tcon_parents, 0x118, 0, 4, 24, 3, BIT(31), CLK_SET_RATE_PARENT); static SUNXI_CCU_M_WITH_MUX_GATE(tcon_tv1_clk, "tcon-tv1", tcon_parents, 0x11c, 0, 4, 24, 3, BIT(31), CLK_SET_RATE_PARENT); static const char * const deinterlace_parents[] = …; static SUNXI_CCU_M_WITH_MUX_GATE(deinterlace_clk, "deinterlace", deinterlace_parents, 0x124, 0, 4, 24, 3, BIT(31), 0); static const char * const csi_mclk_parents[] = …; static SUNXI_CCU_M_WITH_MUX_GATE(csi1_mclk_clk, "csi1-mclk", csi_mclk_parents, 0x130, 0, 5, 8, 3, BIT(15), 0); static const char * const csi_sclk_parents[] = …; static SUNXI_CCU_M_WITH_MUX_GATE(csi_sclk_clk, "csi-sclk", csi_sclk_parents, 0x134, 16, 4, 24, 3, BIT(31), 0); static SUNXI_CCU_M_WITH_MUX_GATE(csi0_mclk_clk, "csi0-mclk", csi_mclk_parents, 0x134, 0, 5, 8, 3, BIT(15), 0); static SUNXI_CCU_M_WITH_GATE(ve_clk, "ve", "pll-ve", 0x13c, 16, 3, BIT(31), CLK_SET_RATE_PARENT); static SUNXI_CCU_GATE(codec_clk, "codec", "pll-audio", 0x140, BIT(31), CLK_SET_RATE_PARENT); static SUNXI_CCU_GATE(avs_clk, "avs", "osc24M", 0x144, BIT(31), 0); static const char * const hdmi_parents[] = …; static SUNXI_CCU_M_WITH_MUX_GATE(hdmi_clk, "hdmi", hdmi_parents, 0x150, 0, 4, 24, 2, BIT(31), CLK_SET_RATE_PARENT); static SUNXI_CCU_GATE(hdmi_slow_clk, "hdmi-slow", "osc24M", 0x154, BIT(31), 0); /* * In the SoC's user manual, the P factor is mentioned, but not used in * the frequency formula. * * Here the factor is included, according to the BSP kernel source, * which contains the P factor of this clock. */ static const char * const mbus_parents[] = …; static SUNXI_CCU_MP_WITH_MUX_GATE(mbus_clk, "mbus", mbus_parents, 0x15c, 0, 4, /* M */ 16, 2, /* P */ 24, 2, /* mux */ BIT(31), /* gate */ CLK_IS_CRITICAL); static const char * const dsi_dphy_parents[] = …; static SUNXI_CCU_M_WITH_MUX_GATE(dsi_dphy_clk, "dsi-dphy", dsi_dphy_parents, 0x168, 0, 4, 8, 2, BIT(15), 0); static SUNXI_CCU_M_WITH_MUX_GATE(tve0_clk, "tve0", tcon_parents, 0x180, 0, 4, 24, 3, BIT(31), 0); static SUNXI_CCU_M_WITH_MUX_GATE(tve1_clk, "tve1", tcon_parents, 0x184, 0, 4, 24, 3, BIT(31), 0); static const char * const tvd_parents[] = …; static SUNXI_CCU_M_WITH_MUX_GATE(tvd0_clk, "tvd0", tvd_parents, 0x188, 0, 4, 24, 3, BIT(31), 0); static SUNXI_CCU_M_WITH_MUX_GATE(tvd1_clk, "tvd1", tvd_parents, 0x18c, 0, 4, 24, 3, BIT(31), 0); static SUNXI_CCU_M_WITH_MUX_GATE(tvd2_clk, "tvd2", tvd_parents, 0x190, 0, 4, 24, 3, BIT(31), 0); static SUNXI_CCU_M_WITH_MUX_GATE(tvd3_clk, "tvd3", tvd_parents, 0x194, 0, 4, 24, 3, BIT(31), 0); static SUNXI_CCU_M_WITH_GATE(gpu_clk, "gpu", "pll-gpu", 0x1a0, 0, 3, BIT(31), CLK_SET_RATE_PARENT); static const char * const out_parents[] = …; static const struct ccu_mux_fixed_prediv out_predivs[] = …; static struct ccu_mp outa_clk = …; static struct ccu_mp outb_clk = …; static struct ccu_common *sun8i_r40_ccu_clks[] = …; /* Fixed Factor clocks */ static CLK_FIXED_FACTOR_FW_NAME(osc12M_clk, "osc12M", "hosc", 2, 1, 0); static const struct clk_hw *clk_parent_pll_audio[] = …; /* We hardcode the divider to 1 for now */ static CLK_FIXED_FACTOR_HWS(pll_audio_clk, "pll-audio", clk_parent_pll_audio, 1, 1, CLK_SET_RATE_PARENT); static CLK_FIXED_FACTOR_HWS(pll_audio_2x_clk, "pll-audio-2x", clk_parent_pll_audio, 2, 1, CLK_SET_RATE_PARENT); static CLK_FIXED_FACTOR_HWS(pll_audio_4x_clk, "pll-audio-4x", clk_parent_pll_audio, 1, 1, CLK_SET_RATE_PARENT); static CLK_FIXED_FACTOR_HWS(pll_audio_8x_clk, "pll-audio-8x", clk_parent_pll_audio, 1, 2, CLK_SET_RATE_PARENT); static CLK_FIXED_FACTOR_HW(pll_periph0_2x_clk, "pll-periph0-2x", &pll_periph0_clk.common.hw, 1, 2, 0); static CLK_FIXED_FACTOR_HW(pll_periph1_2x_clk, "pll-periph1-2x", &pll_periph1_clk.common.hw, 1, 2, 0); static CLK_FIXED_FACTOR_HW(pll_video0_2x_clk, "pll-video0-2x", &pll_video0_clk.common.hw, 1, 2, 0); static CLK_FIXED_FACTOR_HW(pll_video1_2x_clk, "pll-video1-2x", &pll_video1_clk.common.hw, 1, 2, 0); static struct clk_hw_onecell_data sun8i_r40_hw_clks = …; static struct ccu_reset_map sun8i_r40_ccu_resets[] = …; static const struct sunxi_ccu_desc sun8i_r40_ccu_desc = …; static struct ccu_pll_nb sun8i_r40_pll_cpu_nb = …; static struct ccu_mux_nb sun8i_r40_cpu_nb = …; /* * Add a regmap for the GMAC driver (dwmac-sun8i) to access the * GMAC configuration register. * Only this register is allowed to be written, in order to * prevent overriding critical clock configuration. */ #define SUN8I_R40_GMAC_CFG_REG … static bool sun8i_r40_ccu_regmap_accessible_reg(struct device *dev, unsigned int reg) { … } static const struct regmap_config sun8i_r40_ccu_regmap_config = …; #define SUN8I_R40_SYS_32K_CLK_REG … #define SUN8I_R40_SYS_32K_CLK_KEY … static int sun8i_r40_ccu_probe(struct platform_device *pdev) { … } static const struct of_device_id sun8i_r40_ccu_ids[] = …; MODULE_DEVICE_TABLE(of, sun8i_r40_ccu_ids); static struct platform_driver sun8i_r40_ccu_driver = …; module_platform_driver(…) …; MODULE_IMPORT_NS(…); MODULE_DESCRIPTION(…) …; MODULE_LICENSE(…) …;
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