/* SPDX-License-Identifier: GPL-2.0-or-later */ /* * Copyright 2016 Chen-Yu Tsai * * Chen-Yu Tsai <[email protected]> */ #ifndef _CCU_SUN9I_A80_H_ #define _CCU_SUN9I_A80_H_ #include <dt-bindings/clock/sun9i-a80-ccu.h> #include <dt-bindings/reset/sun9i-a80-ccu.h> #define CLK_PLL_C0CPUX … #define CLK_PLL_C1CPUX … /* pll-audio and pll-periph0 are exported to the PRCM block */ #define CLK_PLL_VE … #define CLK_PLL_DDR … #define CLK_PLL_VIDEO0 … #define CLK_PLL_VIDEO1 … #define CLK_PLL_GPU … #define CLK_PLL_DE … #define CLK_PLL_ISP … #define CLK_PLL_PERIPH1 … /* The CPUX clocks are exported */ #define CLK_ATB0 … #define CLK_AXI0 … #define CLK_ATB1 … #define CLK_AXI1 … #define CLK_GTBUS … #define CLK_AHB0 … #define CLK_AHB1 … #define CLK_AHB2 … #define CLK_APB0 … #define CLK_APB1 … #define CLK_CCI400 … #define CLK_ATS … #define CLK_TRACE … /* module clocks and bus gates exported */ #define CLK_NUMBER … #endif /* _CCU_SUN9I_A80_H_ */
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