// SPDX-License-Identifier: GPL-2.0-only /* * Copyright (c) 2016 Chen-Yu Tsai. All rights reserved. */ #include <linux/clk-provider.h> #include <linux/io.h> #include <linux/module.h> #include <linux/platform_device.h> #include "ccu_common.h" #include "ccu_reset.h" #include "ccu_div.h" #include "ccu_gate.h" #include "ccu_mp.h" #include "ccu_nkmp.h" #include "ccu_nm.h" #include "ccu_phase.h" #include "ccu-sun9i-a80.h" #define CCU_SUN9I_LOCK_REG … /* * The CPU PLLs are actually NP clocks, with P being /1 or /4. However * P should only be used for output frequencies lower than 228 MHz. * Neither mainline Linux, U-boot, nor the vendor BSPs use these. * * For now we can just model it as a multiplier clock, and force P to /1. */ #define SUN9I_A80_PLL_C0CPUX_REG … #define SUN9I_A80_PLL_C1CPUX_REG … static struct ccu_mult pll_c0cpux_clk = …; static struct ccu_mult pll_c1cpux_clk = …; /* * The Audio PLL has d1, d2 dividers in addition to the usual N, M * factors. Since we only need 2 frequencies from this PLL: 22.5792 MHz * and 24.576 MHz, ignore them for now. Enforce d1 = 0 and d2 = 0. */ #define SUN9I_A80_PLL_AUDIO_REG … static struct ccu_nm pll_audio_clk = …; /* Some PLLs are input * N / div1 / div2. Model them as NKMP with no K */ static struct ccu_nkmp pll_periph0_clk = …; static struct ccu_nkmp pll_ve_clk = …; static struct ccu_nkmp pll_ddr_clk = …; static struct ccu_nm pll_video0_clk = …; static struct ccu_nkmp pll_video1_clk = …; static struct ccu_nkmp pll_gpu_clk = …; static struct ccu_nkmp pll_de_clk = …; static struct ccu_nkmp pll_isp_clk = …; static struct ccu_nkmp pll_periph1_clk = …; static const char * const c0cpux_parents[] = …; static SUNXI_CCU_MUX(c0cpux_clk, "c0cpux", c0cpux_parents, 0x50, 0, 1, CLK_SET_RATE_PARENT | CLK_IS_CRITICAL); static const char * const c1cpux_parents[] = …; static SUNXI_CCU_MUX(c1cpux_clk, "c1cpux", c1cpux_parents, 0x50, 8, 1, CLK_SET_RATE_PARENT | CLK_IS_CRITICAL); static struct clk_div_table axi_div_table[] = …; static SUNXI_CCU_M(atb0_clk, "atb0", "c0cpux", 0x054, 8, 2, 0); static SUNXI_CCU_DIV_TABLE(axi0_clk, "axi0", "c0cpux", 0x054, 0, 3, axi_div_table, 0); static SUNXI_CCU_M(atb1_clk, "atb1", "c1cpux", 0x058, 8, 2, 0); static SUNXI_CCU_DIV_TABLE(axi1_clk, "axi1", "c1cpux", 0x058, 0, 3, axi_div_table, 0); static const char * const gtbus_parents[] = …; static SUNXI_CCU_M_WITH_MUX(gtbus_clk, "gtbus", gtbus_parents, 0x05c, 0, 2, 24, 2, CLK_IS_CRITICAL); static const char * const ahb_parents[] = …; static struct ccu_div ahb0_clk = …; static struct ccu_div ahb1_clk = …; static struct ccu_div ahb2_clk = …; static const char * const apb_parents[] = …; static struct ccu_div apb0_clk = …; static struct ccu_div apb1_clk = …; static struct ccu_div cci400_clk = …; static SUNXI_CCU_M_WITH_MUX_GATE(ats_clk, "ats", apb_parents, 0x080, 0, 3, 24, 2, BIT(31), 0); static SUNXI_CCU_M_WITH_MUX_GATE(trace_clk, "trace", apb_parents, 0x084, 0, 3, 24, 2, BIT(31), 0); static const char * const out_parents[] = …; static const struct ccu_mux_fixed_prediv out_prediv = …; static struct ccu_mp out_a_clk = …; static struct ccu_mp out_b_clk = …; static const char * const mod0_default_parents[] = …; static SUNXI_CCU_MP_WITH_MUX_GATE(nand0_0_clk, "nand0-0", mod0_default_parents, 0x400, 0, 4, /* M */ 16, 2, /* P */ 24, 4, /* mux */ BIT(31), /* gate */ 0); static SUNXI_CCU_MP_WITH_MUX_GATE(nand0_1_clk, "nand0-1", mod0_default_parents, 0x404, 0, 4, /* M */ 16, 2, /* P */ 24, 4, /* mux */ BIT(31), /* gate */ 0); static SUNXI_CCU_MP_WITH_MUX_GATE(nand1_0_clk, "nand1-0", mod0_default_parents, 0x408, 0, 4, /* M */ 16, 2, /* P */ 24, 4, /* mux */ BIT(31), /* gate */ 0); static SUNXI_CCU_MP_WITH_MUX_GATE(nand1_1_clk, "nand1-1", mod0_default_parents, 0x40c, 0, 4, /* M */ 16, 2, /* P */ 24, 4, /* mux */ BIT(31), /* gate */ 0); static SUNXI_CCU_MP_WITH_MUX_GATE(mmc0_clk, "mmc0", mod0_default_parents, 0x410, 0, 4, /* M */ 16, 2, /* P */ 24, 4, /* mux */ BIT(31), /* gate */ 0); static SUNXI_CCU_PHASE(mmc0_sample_clk, "mmc0-sample", "mmc0", 0x410, 20, 3, 0); static SUNXI_CCU_PHASE(mmc0_output_clk, "mmc0-output", "mmc0", 0x410, 8, 3, 0); static SUNXI_CCU_MP_WITH_MUX_GATE(mmc1_clk, "mmc1", mod0_default_parents, 0x414, 0, 4, /* M */ 16, 2, /* P */ 24, 4, /* mux */ BIT(31), /* gate */ 0); static SUNXI_CCU_PHASE(mmc1_sample_clk, "mmc1-sample", "mmc1", 0x414, 20, 3, 0); static SUNXI_CCU_PHASE(mmc1_output_clk, "mmc1-output", "mmc1", 0x414, 8, 3, 0); static SUNXI_CCU_MP_WITH_MUX_GATE(mmc2_clk, "mmc2", mod0_default_parents, 0x418, 0, 4, /* M */ 16, 2, /* P */ 24, 4, /* mux */ BIT(31), /* gate */ 0); static SUNXI_CCU_PHASE(mmc2_sample_clk, "mmc2-sample", "mmc2", 0x418, 20, 3, 0); static SUNXI_CCU_PHASE(mmc2_output_clk, "mmc2-output", "mmc2", 0x418, 8, 3, 0); static SUNXI_CCU_MP_WITH_MUX_GATE(mmc3_clk, "mmc3", mod0_default_parents, 0x41c, 0, 4, /* M */ 16, 2, /* P */ 24, 4, /* mux */ BIT(31), /* gate */ 0); static SUNXI_CCU_PHASE(mmc3_sample_clk, "mmc3-sample", "mmc3", 0x41c, 20, 3, 0); static SUNXI_CCU_PHASE(mmc3_output_clk, "mmc3-output", "mmc3", 0x41c, 8, 3, 0); static SUNXI_CCU_MP_WITH_MUX_GATE(ts_clk, "ts", mod0_default_parents, 0x428, 0, 4, /* M */ 16, 2, /* P */ 24, 4, /* mux */ BIT(31), /* gate */ 0); static const char * const ss_parents[] = …; static const u8 ss_table[] = …; static struct ccu_mp ss_clk = …; static SUNXI_CCU_MP_WITH_MUX_GATE(spi0_clk, "spi0", mod0_default_parents, 0x430, 0, 4, /* M */ 16, 2, /* P */ 24, 4, /* mux */ BIT(31), /* gate */ 0); static SUNXI_CCU_MP_WITH_MUX_GATE(spi1_clk, "spi1", mod0_default_parents, 0x434, 0, 4, /* M */ 16, 2, /* P */ 24, 4, /* mux */ BIT(31), /* gate */ 0); static SUNXI_CCU_MP_WITH_MUX_GATE(spi2_clk, "spi2", mod0_default_parents, 0x438, 0, 4, /* M */ 16, 2, /* P */ 24, 4, /* mux */ BIT(31), /* gate */ 0); static SUNXI_CCU_MP_WITH_MUX_GATE(spi3_clk, "spi3", mod0_default_parents, 0x43c, 0, 4, /* M */ 16, 2, /* P */ 24, 4, /* mux */ BIT(31), /* gate */ 0); static SUNXI_CCU_M_WITH_GATE(i2s0_clk, "i2s0", "pll-audio", 0x440, 0, 4, BIT(31), CLK_SET_RATE_PARENT); static SUNXI_CCU_M_WITH_GATE(i2s1_clk, "i2s1", "pll-audio", 0x444, 0, 4, BIT(31), CLK_SET_RATE_PARENT); static SUNXI_CCU_M_WITH_GATE(spdif_clk, "spdif", "pll-audio", 0x44c, 0, 4, BIT(31), CLK_SET_RATE_PARENT); static const char * const sdram_parents[] = …; static const u8 sdram_table[] = …; static SUNXI_CCU_M_WITH_MUX_TABLE_GATE(sdram_clk, "sdram", sdram_parents, sdram_table, 0x484, 8, 4, /* M */ 12, 4, /* mux */ 0, /* no gate */ CLK_IS_CRITICAL); static SUNXI_CCU_M_WITH_GATE(de_clk, "de", "pll-de", 0x490, 0, 4, BIT(31), CLK_SET_RATE_PARENT); static SUNXI_CCU_GATE(edp_clk, "edp", "osc24M", 0x494, BIT(31), 0); static const char * const mp_parents[] = …; static const u8 mp_table[] = …; static SUNXI_CCU_M_WITH_MUX_TABLE_GATE(mp_clk, "mp", mp_parents, mp_table, 0x498, 0, 4, /* M */ 24, 4, /* mux */ BIT(31), /* gate */ 0); static const char * const display_parents[] = …; static const u8 display_table[] = …; static SUNXI_CCU_M_WITH_MUX_TABLE_GATE(lcd0_clk, "lcd0", display_parents, display_table, 0x49c, 0, 4, /* M */ 24, 4, /* mux */ BIT(31), /* gate */ CLK_SET_RATE_NO_REPARENT | CLK_SET_RATE_PARENT); static SUNXI_CCU_M_WITH_MUX_TABLE_GATE(lcd1_clk, "lcd1", display_parents, display_table, 0x4a0, 0, 4, /* M */ 24, 4, /* mux */ BIT(31), /* gate */ CLK_SET_RATE_NO_REPARENT | CLK_SET_RATE_PARENT); static SUNXI_CCU_M_WITH_MUX_TABLE_GATE(mipi_dsi0_clk, "mipi-dsi0", display_parents, display_table, 0x4a8, 0, 4, /* M */ 24, 4, /* mux */ BIT(31), /* gate */ CLK_SET_RATE_PARENT); static const char * const mipi_dsi1_parents[] = …; static const u8 mipi_dsi1_table[] = …; static SUNXI_CCU_M_WITH_MUX_TABLE_GATE(mipi_dsi1_clk, "mipi-dsi1", mipi_dsi1_parents, mipi_dsi1_table, 0x4ac, 0, 4, /* M */ 24, 4, /* mux */ BIT(31), /* gate */ CLK_SET_RATE_PARENT); static SUNXI_CCU_M_WITH_MUX_TABLE_GATE(hdmi_clk, "hdmi", display_parents, display_table, 0x4b0, 0, 4, /* M */ 24, 4, /* mux */ BIT(31), /* gate */ CLK_SET_RATE_NO_REPARENT | CLK_SET_RATE_PARENT); static SUNXI_CCU_GATE(hdmi_slow_clk, "hdmi-slow", "osc24M", 0x4b4, BIT(31), 0); static SUNXI_CCU_M_WITH_GATE(mipi_csi_clk, "mipi-csi", "osc24M", 0x4bc, 0, 4, BIT(31), 0); static SUNXI_CCU_M_WITH_GATE(csi_isp_clk, "csi-isp", "pll-isp", 0x4c0, 0, 4, BIT(31), CLK_SET_RATE_PARENT); static SUNXI_CCU_GATE(csi_misc_clk, "csi-misc", "osc24M", 0x4c0, BIT(16), 0); static SUNXI_CCU_M_WITH_MUX_TABLE_GATE(csi0_mclk_clk, "csi0-mclk", mipi_dsi1_parents, mipi_dsi1_table, 0x4c4, 0, 4, /* M */ 24, 4, /* mux */ BIT(31), /* gate */ CLK_SET_RATE_PARENT); static SUNXI_CCU_M_WITH_MUX_TABLE_GATE(csi1_mclk_clk, "csi1-mclk", mipi_dsi1_parents, mipi_dsi1_table, 0x4c8, 0, 4, /* M */ 24, 4, /* mux */ BIT(31), /* gate */ CLK_SET_RATE_PARENT); static const char * const fd_parents[] = …; static const u8 fd_table[] = …; static SUNXI_CCU_M_WITH_MUX_TABLE_GATE(fd_clk, "fd", fd_parents, fd_table, 0x4cc, 0, 4, /* M */ 24, 4, /* mux */ BIT(31), /* gate */ 0); static SUNXI_CCU_M_WITH_GATE(ve_clk, "ve", "pll-ve", 0x4d0, 16, 3, BIT(31), CLK_SET_RATE_PARENT); static SUNXI_CCU_GATE(avs_clk, "avs", "osc24M", 0x4d4, BIT(31), 0); static SUNXI_CCU_M_WITH_GATE(gpu_core_clk, "gpu-core", "pll-gpu", 0x4f0, 0, 3, BIT(31), CLK_SET_RATE_PARENT); static SUNXI_CCU_M_WITH_GATE(gpu_memory_clk, "gpu-memory", "pll-gpu", 0x4f4, 0, 3, BIT(31), CLK_SET_RATE_PARENT); static const char * const gpu_axi_parents[] = …; static const u8 gpu_axi_table[] = …; static SUNXI_CCU_M_WITH_MUX_TABLE_GATE(gpu_axi_clk, "gpu-axi", gpu_axi_parents, gpu_axi_table, 0x4f8, 0, 4, /* M */ 24, 4, /* mux */ BIT(31), /* gate */ CLK_SET_RATE_PARENT); static SUNXI_CCU_M_WITH_GATE(sata_clk, "sata", "pll-periph0", 0x500, 0, 4, BIT(31), 0); static SUNXI_CCU_M_WITH_GATE(ac97_clk, "ac97", "pll-audio", 0x504, 0, 4, BIT(31), CLK_SET_RATE_PARENT); static SUNXI_CCU_M_WITH_MUX_GATE(mipi_hsi_clk, "mipi-hsi", mod0_default_parents, 0x508, 0, 4, /* M */ 24, 4, /* mux */ BIT(31), /* gate */ 0); static const char * const gpadc_parents[] = …; static const u8 gpadc_table[] = …; static struct ccu_mp gpadc_clk = …; static const char * const cir_tx_parents[] = …; static const u8 cir_tx_table[] = …; static struct ccu_mp cir_tx_clk = …; /* AHB0 bus gates */ static SUNXI_CCU_GATE(bus_fd_clk, "bus-fd", "ahb0", 0x580, BIT(0), 0); static SUNXI_CCU_GATE(bus_ve_clk, "bus-ve", "ahb0", 0x580, BIT(1), 0); static SUNXI_CCU_GATE(bus_gpu_ctrl_clk, "bus-gpu-ctrl", "ahb0", 0x580, BIT(3), 0); static SUNXI_CCU_GATE(bus_ss_clk, "bus-ss", "ahb0", 0x580, BIT(5), 0); static SUNXI_CCU_GATE(bus_mmc_clk, "bus-mmc", "ahb0", 0x580, BIT(8), 0); static SUNXI_CCU_GATE(bus_nand0_clk, "bus-nand0", "ahb0", 0x580, BIT(12), 0); static SUNXI_CCU_GATE(bus_nand1_clk, "bus-nand1", "ahb0", 0x580, BIT(13), 0); static SUNXI_CCU_GATE(bus_sdram_clk, "bus-sdram", "ahb0", 0x580, BIT(14), 0); static SUNXI_CCU_GATE(bus_mipi_hsi_clk, "bus-mipi-hsi", "ahb0", 0x580, BIT(15), 0); static SUNXI_CCU_GATE(bus_sata_clk, "bus-sata", "ahb0", 0x580, BIT(16), 0); static SUNXI_CCU_GATE(bus_ts_clk, "bus-ts", "ahb0", 0x580, BIT(18), 0); static SUNXI_CCU_GATE(bus_spi0_clk, "bus-spi0", "ahb0", 0x580, BIT(20), 0); static SUNXI_CCU_GATE(bus_spi1_clk, "bus-spi1", "ahb0", 0x580, BIT(21), 0); static SUNXI_CCU_GATE(bus_spi2_clk, "bus-spi2", "ahb0", 0x580, BIT(22), 0); static SUNXI_CCU_GATE(bus_spi3_clk, "bus-spi3", "ahb0", 0x580, BIT(23), 0); /* AHB1 bus gates */ static SUNXI_CCU_GATE(bus_otg_clk, "bus-otg", "ahb1", 0x584, BIT(0), 0); static SUNXI_CCU_GATE(bus_usb_clk, "bus-usb", "ahb1", 0x584, BIT(1), 0); static SUNXI_CCU_GATE(bus_gmac_clk, "bus-gmac", "ahb1", 0x584, BIT(17), 0); static SUNXI_CCU_GATE(bus_msgbox_clk, "bus-msgbox", "ahb1", 0x584, BIT(21), 0); static SUNXI_CCU_GATE(bus_spinlock_clk, "bus-spinlock", "ahb1", 0x584, BIT(22), 0); static SUNXI_CCU_GATE(bus_hstimer_clk, "bus-hstimer", "ahb1", 0x584, BIT(23), 0); static SUNXI_CCU_GATE(bus_dma_clk, "bus-dma", "ahb1", 0x584, BIT(24), 0); /* AHB2 bus gates */ static SUNXI_CCU_GATE(bus_lcd0_clk, "bus-lcd0", "ahb2", 0x588, BIT(0), 0); static SUNXI_CCU_GATE(bus_lcd1_clk, "bus-lcd1", "ahb2", 0x588, BIT(1), 0); static SUNXI_CCU_GATE(bus_edp_clk, "bus-edp", "ahb2", 0x588, BIT(2), 0); static SUNXI_CCU_GATE(bus_csi_clk, "bus-csi", "ahb2", 0x588, BIT(4), 0); static SUNXI_CCU_GATE(bus_hdmi_clk, "bus-hdmi", "ahb2", 0x588, BIT(5), 0); static SUNXI_CCU_GATE(bus_de_clk, "bus-de", "ahb2", 0x588, BIT(7), 0); static SUNXI_CCU_GATE(bus_mp_clk, "bus-mp", "ahb2", 0x588, BIT(8), 0); static SUNXI_CCU_GATE(bus_mipi_dsi_clk, "bus-mipi-dsi", "ahb2", 0x588, BIT(11), 0); /* APB0 bus gates */ static SUNXI_CCU_GATE(bus_spdif_clk, "bus-spdif", "apb0", 0x590, BIT(1), 0); static SUNXI_CCU_GATE(bus_pio_clk, "bus-pio", "apb0", 0x590, BIT(5), 0); static SUNXI_CCU_GATE(bus_ac97_clk, "bus-ac97", "apb0", 0x590, BIT(11), 0); static SUNXI_CCU_GATE(bus_i2s0_clk, "bus-i2s0", "apb0", 0x590, BIT(12), 0); static SUNXI_CCU_GATE(bus_i2s1_clk, "bus-i2s1", "apb0", 0x590, BIT(13), 0); static SUNXI_CCU_GATE(bus_lradc_clk, "bus-lradc", "apb0", 0x590, BIT(15), 0); static SUNXI_CCU_GATE(bus_gpadc_clk, "bus-gpadc", "apb0", 0x590, BIT(17), 0); static SUNXI_CCU_GATE(bus_twd_clk, "bus-twd", "apb0", 0x590, BIT(18), 0); static SUNXI_CCU_GATE(bus_cir_tx_clk, "bus-cir-tx", "apb0", 0x590, BIT(19), 0); /* APB1 bus gates */ static SUNXI_CCU_GATE(bus_i2c0_clk, "bus-i2c0", "apb1", 0x594, BIT(0), 0); static SUNXI_CCU_GATE(bus_i2c1_clk, "bus-i2c1", "apb1", 0x594, BIT(1), 0); static SUNXI_CCU_GATE(bus_i2c2_clk, "bus-i2c2", "apb1", 0x594, BIT(2), 0); static SUNXI_CCU_GATE(bus_i2c3_clk, "bus-i2c3", "apb1", 0x594, BIT(3), 0); static SUNXI_CCU_GATE(bus_i2c4_clk, "bus-i2c4", "apb1", 0x594, BIT(4), 0); static SUNXI_CCU_GATE(bus_uart0_clk, "bus-uart0", "apb1", 0x594, BIT(16), 0); static SUNXI_CCU_GATE(bus_uart1_clk, "bus-uart1", "apb1", 0x594, BIT(17), 0); static SUNXI_CCU_GATE(bus_uart2_clk, "bus-uart2", "apb1", 0x594, BIT(18), 0); static SUNXI_CCU_GATE(bus_uart3_clk, "bus-uart3", "apb1", 0x594, BIT(19), 0); static SUNXI_CCU_GATE(bus_uart4_clk, "bus-uart4", "apb1", 0x594, BIT(20), 0); static SUNXI_CCU_GATE(bus_uart5_clk, "bus-uart5", "apb1", 0x594, BIT(21), 0); static struct ccu_common *sun9i_a80_ccu_clks[] = …; static struct clk_hw_onecell_data sun9i_a80_hw_clks = …; static struct ccu_reset_map sun9i_a80_ccu_resets[] = …; static const struct sunxi_ccu_desc sun9i_a80_ccu_desc = …; #define SUN9I_A80_PLL_P_SHIFT … #define SUN9I_A80_PLL_N_SHIFT … #define SUN9I_A80_PLL_N_WIDTH … static void sun9i_a80_cpu_pll_fixup(void __iomem *reg) { … } static int sun9i_a80_ccu_probe(struct platform_device *pdev) { … } static const struct of_device_id sun9i_a80_ccu_ids[] = …; MODULE_DEVICE_TABLE(of, sun9i_a80_ccu_ids); static struct platform_driver sun9i_a80_ccu_driver = …; module_platform_driver(…) …; MODULE_IMPORT_NS(…); MODULE_DESCRIPTION(…) …; MODULE_LICENSE(…) …;
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