// SPDX-License-Identifier: GPL-2.0 /* Nehalem/SandBridge/Haswell/Broadwell/Skylake uncore support */ #include "uncore.h" #include "uncore_discovery.h" /* Uncore IMC PCI IDs */ #define PCI_DEVICE_ID_INTEL_SNB_IMC … #define PCI_DEVICE_ID_INTEL_IVB_IMC … #define PCI_DEVICE_ID_INTEL_IVB_E3_IMC … #define PCI_DEVICE_ID_INTEL_HSW_IMC … #define PCI_DEVICE_ID_INTEL_HSW_U_IMC … #define PCI_DEVICE_ID_INTEL_BDW_IMC … #define PCI_DEVICE_ID_INTEL_SKL_U_IMC … #define PCI_DEVICE_ID_INTEL_SKL_Y_IMC … #define PCI_DEVICE_ID_INTEL_SKL_HD_IMC … #define PCI_DEVICE_ID_INTEL_SKL_HQ_IMC … #define PCI_DEVICE_ID_INTEL_SKL_SD_IMC … #define PCI_DEVICE_ID_INTEL_SKL_SQ_IMC … #define PCI_DEVICE_ID_INTEL_SKL_E3_IMC … #define PCI_DEVICE_ID_INTEL_KBL_Y_IMC … #define PCI_DEVICE_ID_INTEL_KBL_U_IMC … #define PCI_DEVICE_ID_INTEL_KBL_UQ_IMC … #define PCI_DEVICE_ID_INTEL_KBL_SD_IMC … #define PCI_DEVICE_ID_INTEL_KBL_SQ_IMC … #define PCI_DEVICE_ID_INTEL_KBL_HQ_IMC … #define PCI_DEVICE_ID_INTEL_KBL_WQ_IMC … #define PCI_DEVICE_ID_INTEL_CFL_2U_IMC … #define PCI_DEVICE_ID_INTEL_CFL_4U_IMC … #define PCI_DEVICE_ID_INTEL_CFL_4H_IMC … #define PCI_DEVICE_ID_INTEL_CFL_6H_IMC … #define PCI_DEVICE_ID_INTEL_CFL_2S_D_IMC … #define PCI_DEVICE_ID_INTEL_CFL_4S_D_IMC … #define PCI_DEVICE_ID_INTEL_CFL_6S_D_IMC … #define PCI_DEVICE_ID_INTEL_CFL_8S_D_IMC … #define PCI_DEVICE_ID_INTEL_CFL_4S_W_IMC … #define PCI_DEVICE_ID_INTEL_CFL_6S_W_IMC … #define PCI_DEVICE_ID_INTEL_CFL_8S_W_IMC … #define PCI_DEVICE_ID_INTEL_CFL_4S_S_IMC … #define PCI_DEVICE_ID_INTEL_CFL_6S_S_IMC … #define PCI_DEVICE_ID_INTEL_CFL_8S_S_IMC … #define PCI_DEVICE_ID_INTEL_AML_YD_IMC … #define PCI_DEVICE_ID_INTEL_AML_YQ_IMC … #define PCI_DEVICE_ID_INTEL_WHL_UQ_IMC … #define PCI_DEVICE_ID_INTEL_WHL_4_UQ_IMC … #define PCI_DEVICE_ID_INTEL_WHL_UD_IMC … #define PCI_DEVICE_ID_INTEL_CML_H1_IMC … #define PCI_DEVICE_ID_INTEL_CML_H2_IMC … #define PCI_DEVICE_ID_INTEL_CML_H3_IMC … #define PCI_DEVICE_ID_INTEL_CML_U1_IMC … #define PCI_DEVICE_ID_INTEL_CML_U2_IMC … #define PCI_DEVICE_ID_INTEL_CML_U3_IMC … #define PCI_DEVICE_ID_INTEL_CML_S1_IMC … #define PCI_DEVICE_ID_INTEL_CML_S2_IMC … #define PCI_DEVICE_ID_INTEL_CML_S3_IMC … #define PCI_DEVICE_ID_INTEL_CML_S4_IMC … #define PCI_DEVICE_ID_INTEL_CML_S5_IMC … #define PCI_DEVICE_ID_INTEL_ICL_U_IMC … #define PCI_DEVICE_ID_INTEL_ICL_U2_IMC … #define PCI_DEVICE_ID_INTEL_TGL_U1_IMC … #define PCI_DEVICE_ID_INTEL_TGL_U2_IMC … #define PCI_DEVICE_ID_INTEL_TGL_U3_IMC … #define PCI_DEVICE_ID_INTEL_TGL_U4_IMC … #define PCI_DEVICE_ID_INTEL_TGL_H_IMC … #define PCI_DEVICE_ID_INTEL_RKL_1_IMC … #define PCI_DEVICE_ID_INTEL_RKL_2_IMC … #define PCI_DEVICE_ID_INTEL_ADL_1_IMC … #define PCI_DEVICE_ID_INTEL_ADL_2_IMC … #define PCI_DEVICE_ID_INTEL_ADL_3_IMC … #define PCI_DEVICE_ID_INTEL_ADL_4_IMC … #define PCI_DEVICE_ID_INTEL_ADL_5_IMC … #define PCI_DEVICE_ID_INTEL_ADL_6_IMC … #define PCI_DEVICE_ID_INTEL_ADL_7_IMC … #define PCI_DEVICE_ID_INTEL_ADL_8_IMC … #define PCI_DEVICE_ID_INTEL_ADL_9_IMC … #define PCI_DEVICE_ID_INTEL_ADL_10_IMC … #define PCI_DEVICE_ID_INTEL_ADL_11_IMC … #define PCI_DEVICE_ID_INTEL_ADL_12_IMC … #define PCI_DEVICE_ID_INTEL_ADL_13_IMC … #define PCI_DEVICE_ID_INTEL_ADL_14_IMC … #define PCI_DEVICE_ID_INTEL_ADL_15_IMC … #define PCI_DEVICE_ID_INTEL_ADL_16_IMC … #define PCI_DEVICE_ID_INTEL_ADL_17_IMC … #define PCI_DEVICE_ID_INTEL_ADL_18_IMC … #define PCI_DEVICE_ID_INTEL_ADL_19_IMC … #define PCI_DEVICE_ID_INTEL_ADL_20_IMC … #define PCI_DEVICE_ID_INTEL_ADL_21_IMC … #define PCI_DEVICE_ID_INTEL_RPL_1_IMC … #define PCI_DEVICE_ID_INTEL_RPL_2_IMC … #define PCI_DEVICE_ID_INTEL_RPL_3_IMC … #define PCI_DEVICE_ID_INTEL_RPL_4_IMC … #define PCI_DEVICE_ID_INTEL_RPL_5_IMC … #define PCI_DEVICE_ID_INTEL_RPL_6_IMC … #define PCI_DEVICE_ID_INTEL_RPL_7_IMC … #define PCI_DEVICE_ID_INTEL_RPL_8_IMC … #define PCI_DEVICE_ID_INTEL_RPL_9_IMC … #define PCI_DEVICE_ID_INTEL_RPL_10_IMC … #define PCI_DEVICE_ID_INTEL_RPL_11_IMC … #define PCI_DEVICE_ID_INTEL_RPL_12_IMC … #define PCI_DEVICE_ID_INTEL_RPL_13_IMC … #define PCI_DEVICE_ID_INTEL_RPL_14_IMC … #define PCI_DEVICE_ID_INTEL_RPL_15_IMC … #define PCI_DEVICE_ID_INTEL_RPL_16_IMC … #define PCI_DEVICE_ID_INTEL_RPL_17_IMC … #define PCI_DEVICE_ID_INTEL_RPL_18_IMC … #define PCI_DEVICE_ID_INTEL_RPL_19_IMC … #define PCI_DEVICE_ID_INTEL_RPL_20_IMC … #define PCI_DEVICE_ID_INTEL_RPL_21_IMC … #define PCI_DEVICE_ID_INTEL_RPL_22_IMC … #define PCI_DEVICE_ID_INTEL_RPL_23_IMC … #define PCI_DEVICE_ID_INTEL_RPL_24_IMC … #define PCI_DEVICE_ID_INTEL_RPL_25_IMC … #define PCI_DEVICE_ID_INTEL_MTL_1_IMC … #define PCI_DEVICE_ID_INTEL_MTL_2_IMC … #define PCI_DEVICE_ID_INTEL_MTL_3_IMC … #define PCI_DEVICE_ID_INTEL_MTL_4_IMC … #define PCI_DEVICE_ID_INTEL_MTL_5_IMC … #define PCI_DEVICE_ID_INTEL_MTL_6_IMC … #define PCI_DEVICE_ID_INTEL_MTL_7_IMC … #define PCI_DEVICE_ID_INTEL_MTL_8_IMC … #define PCI_DEVICE_ID_INTEL_MTL_9_IMC … #define PCI_DEVICE_ID_INTEL_MTL_10_IMC … #define PCI_DEVICE_ID_INTEL_MTL_11_IMC … #define PCI_DEVICE_ID_INTEL_MTL_12_IMC … #define PCI_DEVICE_ID_INTEL_MTL_13_IMC … #define IMC_UNCORE_DEV(a) … /* SNB event control */ #define SNB_UNC_CTL_EV_SEL_MASK … #define SNB_UNC_CTL_UMASK_MASK … #define SNB_UNC_CTL_EDGE_DET … #define SNB_UNC_CTL_EN … #define SNB_UNC_CTL_INVERT … #define SNB_UNC_CTL_CMASK_MASK … #define NHM_UNC_CTL_CMASK_MASK … #define NHM_UNC_FIXED_CTR_CTL_EN … #define SNB_UNC_RAW_EVENT_MASK … #define NHM_UNC_RAW_EVENT_MASK … /* SNB global control register */ #define SNB_UNC_PERF_GLOBAL_CTL … #define SNB_UNC_FIXED_CTR_CTRL … #define SNB_UNC_FIXED_CTR … /* SNB uncore global control */ #define SNB_UNC_GLOBAL_CTL_CORE_ALL … #define SNB_UNC_GLOBAL_CTL_EN … /* SNB Cbo register */ #define SNB_UNC_CBO_0_PERFEVTSEL0 … #define SNB_UNC_CBO_0_PER_CTR0 … #define SNB_UNC_CBO_MSR_OFFSET … /* SNB ARB register */ #define SNB_UNC_ARB_PER_CTR0 … #define SNB_UNC_ARB_PERFEVTSEL0 … #define SNB_UNC_ARB_MSR_OFFSET … /* NHM global control register */ #define NHM_UNC_PERF_GLOBAL_CTL … #define NHM_UNC_FIXED_CTR … #define NHM_UNC_FIXED_CTR_CTRL … /* NHM uncore global control */ #define NHM_UNC_GLOBAL_CTL_EN_PC_ALL … #define NHM_UNC_GLOBAL_CTL_EN_FC … /* NHM uncore register */ #define NHM_UNC_PERFEVTSEL0 … #define NHM_UNC_UNCORE_PMC0 … /* SKL uncore global control */ #define SKL_UNC_PERF_GLOBAL_CTL … #define SKL_UNC_GLOBAL_CTL_CORE_ALL … /* ICL Cbo register */ #define ICL_UNC_CBO_CONFIG … #define ICL_UNC_NUM_CBO_MASK … #define ICL_UNC_CBO_0_PER_CTR0 … #define ICL_UNC_CBO_MSR_OFFSET … /* ICL ARB register */ #define ICL_UNC_ARB_PER_CTR … #define ICL_UNC_ARB_PERFEVTSEL … /* ADL uncore global control */ #define ADL_UNC_PERF_GLOBAL_CTL … #define ADL_UNC_FIXED_CTR_CTRL … #define ADL_UNC_FIXED_CTR … /* ADL Cbo register */ #define ADL_UNC_CBO_0_PER_CTR0 … #define ADL_UNC_CBO_0_PERFEVTSEL0 … #define ADL_UNC_CTL_THRESHOLD … #define ADL_UNC_RAW_EVENT_MASK … /* ADL ARB register */ #define ADL_UNC_ARB_PER_CTR0 … #define ADL_UNC_ARB_PERFEVTSEL0 … #define ADL_UNC_ARB_MSR_OFFSET … /* MTL Cbo register */ #define MTL_UNC_CBO_0_PER_CTR0 … #define MTL_UNC_CBO_0_PERFEVTSEL0 … /* MTL HAC_ARB register */ #define MTL_UNC_HAC_ARB_CTR … #define MTL_UNC_HAC_ARB_CTRL … /* MTL ARB register */ #define MTL_UNC_ARB_CTR … #define MTL_UNC_ARB_CTRL … /* MTL cNCU register */ #define MTL_UNC_CNCU_FIXED_CTR … #define MTL_UNC_CNCU_FIXED_CTRL … #define MTL_UNC_CNCU_BOX_CTL … /* MTL sNCU register */ #define MTL_UNC_SNCU_FIXED_CTR … #define MTL_UNC_SNCU_FIXED_CTRL … #define MTL_UNC_SNCU_BOX_CTL … /* MTL HAC_CBO register */ #define MTL_UNC_HBO_CTR … #define MTL_UNC_HBO_CTRL … DEFINE_UNCORE_FORMAT_ATTR(…); DEFINE_UNCORE_FORMAT_ATTR(…); DEFINE_UNCORE_FORMAT_ATTR(…); DEFINE_UNCORE_FORMAT_ATTR(…); DEFINE_UNCORE_FORMAT_ATTR(…); DEFINE_UNCORE_FORMAT_ATTR(…); DEFINE_UNCORE_FORMAT_ATTR(…); DEFINE_UNCORE_FORMAT_ATTR(…); /* Sandy Bridge uncore support */ static void snb_uncore_msr_enable_event(struct intel_uncore_box *box, struct perf_event *event) { … } static void snb_uncore_msr_disable_event(struct intel_uncore_box *box, struct perf_event *event) { … } static void snb_uncore_msr_init_box(struct intel_uncore_box *box) { … } static void snb_uncore_msr_enable_box(struct intel_uncore_box *box) { … } static void snb_uncore_msr_exit_box(struct intel_uncore_box *box) { … } static struct uncore_event_desc snb_uncore_events[] = …; static struct attribute *snb_uncore_formats_attr[] = …; static const struct attribute_group snb_uncore_format_group = …; static struct intel_uncore_ops snb_uncore_msr_ops = …; static struct event_constraint snb_uncore_arb_constraints[] = …; static struct intel_uncore_type snb_uncore_cbox = …; static struct intel_uncore_type snb_uncore_arb = …; static struct intel_uncore_type *snb_msr_uncores[] = …; void snb_uncore_cpu_init(void) { … } static void skl_uncore_msr_init_box(struct intel_uncore_box *box) { … } static void skl_uncore_msr_enable_box(struct intel_uncore_box *box) { … } static void skl_uncore_msr_exit_box(struct intel_uncore_box *box) { … } static struct intel_uncore_ops skl_uncore_msr_ops = …; static struct intel_uncore_type skl_uncore_cbox = …; static struct intel_uncore_type *skl_msr_uncores[] = …; void skl_uncore_cpu_init(void) { … } static struct intel_uncore_ops icl_uncore_msr_ops = …; static struct intel_uncore_type icl_uncore_cbox = …; static struct uncore_event_desc icl_uncore_events[] = …; static struct attribute *icl_uncore_clock_formats_attr[] = …; static struct attribute_group icl_uncore_clock_format_group = …; static struct intel_uncore_type icl_uncore_clockbox = …; static struct intel_uncore_type icl_uncore_arb = …; static struct intel_uncore_type *icl_msr_uncores[] = …; static int icl_get_cbox_num(void) { … } void icl_uncore_cpu_init(void) { … } static struct intel_uncore_type *tgl_msr_uncores[] = …; static void rkl_uncore_msr_init_box(struct intel_uncore_box *box) { … } void tgl_uncore_cpu_init(void) { … } static void adl_uncore_msr_init_box(struct intel_uncore_box *box) { … } static void adl_uncore_msr_enable_box(struct intel_uncore_box *box) { … } static void adl_uncore_msr_disable_box(struct intel_uncore_box *box) { … } static void adl_uncore_msr_exit_box(struct intel_uncore_box *box) { … } static struct intel_uncore_ops adl_uncore_msr_ops = …; static struct attribute *adl_uncore_formats_attr[] = …; static const struct attribute_group adl_uncore_format_group = …; static struct intel_uncore_type adl_uncore_cbox = …; static struct intel_uncore_type adl_uncore_arb = …; static struct intel_uncore_type adl_uncore_clockbox = …; static struct intel_uncore_type *adl_msr_uncores[] = …; void adl_uncore_cpu_init(void) { … } static struct intel_uncore_type mtl_uncore_cbox = …; static struct intel_uncore_type mtl_uncore_hac_arb = …; static struct intel_uncore_type mtl_uncore_arb = …; static struct intel_uncore_type mtl_uncore_hac_cbox = …; static void mtl_uncore_msr_init_box(struct intel_uncore_box *box) { … } static struct intel_uncore_ops mtl_uncore_msr_ops = …; static struct intel_uncore_type mtl_uncore_cncu = …; static struct intel_uncore_type mtl_uncore_sncu = …; static struct intel_uncore_type *mtl_msr_uncores[] = …; void mtl_uncore_cpu_init(void) { … } enum { … }; static struct uncore_event_desc snb_uncore_imc_events[] = …; #define SNB_UNCORE_PCI_IMC_EVENT_MASK … #define SNB_UNCORE_PCI_IMC_BAR_OFFSET … /* page size multiple covering all config regs */ #define SNB_UNCORE_PCI_IMC_MAP_SIZE … #define SNB_UNCORE_PCI_IMC_DATA_READS … #define SNB_UNCORE_PCI_IMC_DATA_READS_BASE … #define SNB_UNCORE_PCI_IMC_DATA_WRITES … #define SNB_UNCORE_PCI_IMC_DATA_WRITES_BASE … #define SNB_UNCORE_PCI_IMC_CTR_BASE … /* BW break down- legacy counters */ #define SNB_UNCORE_PCI_IMC_GT_REQUESTS … #define SNB_UNCORE_PCI_IMC_GT_REQUESTS_BASE … #define SNB_UNCORE_PCI_IMC_IA_REQUESTS … #define SNB_UNCORE_PCI_IMC_IA_REQUESTS_BASE … #define SNB_UNCORE_PCI_IMC_IO_REQUESTS … #define SNB_UNCORE_PCI_IMC_IO_REQUESTS_BASE … enum perf_snb_uncore_imc_freerunning_types { … }; static struct freerunning_counters snb_uncore_imc_freerunning[] = …; static struct attribute *snb_uncore_imc_formats_attr[] = …; static const struct attribute_group snb_uncore_imc_format_group = …; static void snb_uncore_imc_init_box(struct intel_uncore_box *box) { … } static void snb_uncore_imc_enable_box(struct intel_uncore_box *box) { … } static void snb_uncore_imc_disable_box(struct intel_uncore_box *box) { … } static void snb_uncore_imc_enable_event(struct intel_uncore_box *box, struct perf_event *event) { … } static void snb_uncore_imc_disable_event(struct intel_uncore_box *box, struct perf_event *event) { … } /* * Keep the custom event_init() function compatible with old event * encoding for free running counters. */ static int snb_uncore_imc_event_init(struct perf_event *event) { … } static int snb_uncore_imc_hw_config(struct intel_uncore_box *box, struct perf_event *event) { … } int snb_pci2phy_map_init(int devid) { … } static u64 snb_uncore_imc_read_counter(struct intel_uncore_box *box, struct perf_event *event) { … } static struct pmu snb_uncore_imc_pmu = …; static struct intel_uncore_ops snb_uncore_imc_ops = …; static struct intel_uncore_type snb_uncore_imc = …; static struct intel_uncore_type *snb_pci_uncores[] = …; static const struct pci_device_id snb_uncore_pci_ids[] = …; static const struct pci_device_id ivb_uncore_pci_ids[] = …; static const struct pci_device_id hsw_uncore_pci_ids[] = …; static const struct pci_device_id bdw_uncore_pci_ids[] = …; static const struct pci_device_id skl_uncore_pci_ids[] = …; static const struct pci_device_id icl_uncore_pci_ids[] = …; static struct pci_driver snb_uncore_pci_driver = …; static struct pci_driver ivb_uncore_pci_driver = …; static struct pci_driver hsw_uncore_pci_driver = …; static struct pci_driver bdw_uncore_pci_driver = …; static struct pci_driver skl_uncore_pci_driver = …; static struct pci_driver icl_uncore_pci_driver = …; struct imc_uncore_pci_dev { … }; #define IMC_DEV(a, d) … static const struct imc_uncore_pci_dev desktop_imc_pci_ids[] = …; #define for_each_imc_pci_id(x, t) … static struct pci_driver *imc_uncore_find_dev(void) { … } static int imc_uncore_pci_init(void) { … } int snb_uncore_pci_init(void) { … } int ivb_uncore_pci_init(void) { … } int hsw_uncore_pci_init(void) { … } int bdw_uncore_pci_init(void) { … } int skl_uncore_pci_init(void) { … } /* end of Sandy Bridge uncore support */ /* Nehalem uncore support */ static void nhm_uncore_msr_disable_box(struct intel_uncore_box *box) { … } static void nhm_uncore_msr_enable_box(struct intel_uncore_box *box) { … } static void nhm_uncore_msr_enable_event(struct intel_uncore_box *box, struct perf_event *event) { … } static struct attribute *nhm_uncore_formats_attr[] = …; static const struct attribute_group nhm_uncore_format_group = …; static struct uncore_event_desc nhm_uncore_events[] = …; static struct intel_uncore_ops nhm_uncore_msr_ops = …; static struct intel_uncore_type nhm_uncore = …; static struct intel_uncore_type *nhm_msr_uncores[] = …; void nhm_uncore_cpu_init(void) { … } /* end of Nehalem uncore support */ /* Tiger Lake MMIO uncore support */ static const struct pci_device_id tgl_uncore_pci_ids[] = …; enum perf_tgl_uncore_imc_freerunning_types { … }; static struct freerunning_counters tgl_l_uncore_imc_freerunning[] = …; static struct freerunning_counters tgl_uncore_imc_freerunning[] = …; static struct uncore_event_desc tgl_uncore_imc_events[] = …; static struct pci_dev *tgl_uncore_get_mc_dev(void) { … } #define TGL_UNCORE_MMIO_IMC_MEM_OFFSET … #define TGL_UNCORE_PCI_IMC_MAP_SIZE … static void __uncore_imc_init_box(struct intel_uncore_box *box, unsigned int base_offset) { … } static void tgl_uncore_imc_freerunning_init_box(struct intel_uncore_box *box) { … } static struct intel_uncore_ops tgl_uncore_imc_freerunning_ops = …; static struct attribute *tgl_uncore_imc_formats_attr[] = …; static const struct attribute_group tgl_uncore_imc_format_group = …; static struct intel_uncore_type tgl_uncore_imc_free_running = …; static struct intel_uncore_type *tgl_mmio_uncores[] = …; void tgl_l_uncore_mmio_init(void) { … } void tgl_uncore_mmio_init(void) { … } /* end of Tiger Lake MMIO uncore support */ /* Alder Lake MMIO uncore support */ #define ADL_UNCORE_IMC_BASE … #define ADL_UNCORE_IMC_MAP_SIZE … #define ADL_UNCORE_IMC_CTR … #define ADL_UNCORE_IMC_CTRL … #define ADL_UNCORE_IMC_GLOBAL_CTL … #define ADL_UNCORE_IMC_BOX_CTL … #define ADL_UNCORE_IMC_FREERUNNING_BASE … #define ADL_UNCORE_IMC_FREERUNNING_MAP_SIZE … #define ADL_UNCORE_IMC_CTL_FRZ … #define ADL_UNCORE_IMC_CTL_RST_CTRL … #define ADL_UNCORE_IMC_CTL_RST_CTRS … #define ADL_UNCORE_IMC_CTL_INT … static void adl_uncore_imc_init_box(struct intel_uncore_box *box) { … } static void adl_uncore_mmio_disable_box(struct intel_uncore_box *box) { … } static void adl_uncore_mmio_enable_box(struct intel_uncore_box *box) { … } static struct intel_uncore_ops adl_uncore_mmio_ops = …; #define ADL_UNC_CTL_CHMASK_MASK … #define ADL_UNC_IMC_EVENT_MASK … static struct attribute *adl_uncore_imc_formats_attr[] = …; static const struct attribute_group adl_uncore_imc_format_group = …; static struct intel_uncore_type adl_uncore_imc = …; enum perf_adl_uncore_imc_freerunning_types { … }; static struct freerunning_counters adl_uncore_imc_freerunning[] = …; static void adl_uncore_imc_freerunning_init_box(struct intel_uncore_box *box) { … } static struct intel_uncore_ops adl_uncore_imc_freerunning_ops = …; static struct intel_uncore_type adl_uncore_imc_free_running = …; static struct intel_uncore_type *adl_mmio_uncores[] = …; void adl_uncore_mmio_init(void) { … } /* end of Alder Lake MMIO uncore support */
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