// SPDX-License-Identifier: GPL-2.0 /* Nehalem-EX/Westmere-EX uncore support */ #include <asm/cpu_device_id.h> #include "uncore.h" /* NHM-EX event control */ #define NHMEX_PMON_CTL_EV_SEL_MASK … #define NHMEX_PMON_CTL_UMASK_MASK … #define NHMEX_PMON_CTL_EN_BIT0 … #define NHMEX_PMON_CTL_EDGE_DET … #define NHMEX_PMON_CTL_PMI_EN … #define NHMEX_PMON_CTL_EN_BIT22 … #define NHMEX_PMON_CTL_INVERT … #define NHMEX_PMON_CTL_TRESH_MASK … #define NHMEX_PMON_RAW_EVENT_MASK … /* NHM-EX Ubox */ #define NHMEX_U_MSR_PMON_GLOBAL_CTL … #define NHMEX_U_MSR_PMON_CTR … #define NHMEX_U_MSR_PMON_EV_SEL … #define NHMEX_U_PMON_GLOBAL_EN … #define NHMEX_U_PMON_GLOBAL_PMI_CORE_SEL … #define NHMEX_U_PMON_GLOBAL_EN_ALL … #define NHMEX_U_PMON_GLOBAL_RST_ALL … #define NHMEX_U_PMON_GLOBAL_FRZ_ALL … #define NHMEX_U_PMON_RAW_EVENT_MASK … /* NHM-EX Cbox */ #define NHMEX_C0_MSR_PMON_GLOBAL_CTL … #define NHMEX_C0_MSR_PMON_CTR0 … #define NHMEX_C0_MSR_PMON_EV_SEL0 … #define NHMEX_C_MSR_OFFSET … /* NHM-EX Bbox */ #define NHMEX_B0_MSR_PMON_GLOBAL_CTL … #define NHMEX_B0_MSR_PMON_CTR0 … #define NHMEX_B0_MSR_PMON_CTL0 … #define NHMEX_B_MSR_OFFSET … #define NHMEX_B0_MSR_MATCH … #define NHMEX_B0_MSR_MASK … #define NHMEX_B1_MSR_MATCH … #define NHMEX_B1_MSR_MASK … #define NHMEX_B_PMON_CTL_EN … #define NHMEX_B_PMON_CTL_EV_SEL_SHIFT … #define NHMEX_B_PMON_CTL_EV_SEL_MASK … #define NHMEX_B_PMON_CTR_SHIFT … #define NHMEX_B_PMON_CTR_MASK … #define NHMEX_B_PMON_RAW_EVENT_MASK … /* NHM-EX Sbox */ #define NHMEX_S0_MSR_PMON_GLOBAL_CTL … #define NHMEX_S0_MSR_PMON_CTR0 … #define NHMEX_S0_MSR_PMON_CTL0 … #define NHMEX_S_MSR_OFFSET … #define NHMEX_S0_MSR_MM_CFG … #define NHMEX_S0_MSR_MATCH … #define NHMEX_S0_MSR_MASK … #define NHMEX_S1_MSR_MM_CFG … #define NHMEX_S1_MSR_MATCH … #define NHMEX_S1_MSR_MASK … #define NHMEX_S_PMON_MM_CFG_EN … #define NHMEX_S_EVENT_TO_R_PROG_EV … /* NHM-EX Mbox */ #define NHMEX_M0_MSR_GLOBAL_CTL … #define NHMEX_M0_MSR_PMU_DSP … #define NHMEX_M0_MSR_PMU_ISS … #define NHMEX_M0_MSR_PMU_MAP … #define NHMEX_M0_MSR_PMU_MSC_THR … #define NHMEX_M0_MSR_PMU_PGT … #define NHMEX_M0_MSR_PMU_PLD … #define NHMEX_M0_MSR_PMU_ZDP_CTL_FVC … #define NHMEX_M0_MSR_PMU_CTL0 … #define NHMEX_M0_MSR_PMU_CNT0 … #define NHMEX_M_MSR_OFFSET … #define NHMEX_M0_MSR_PMU_MM_CFG … #define NHMEX_M1_MSR_PMU_MM_CFG … #define NHMEX_M_PMON_MM_CFG_EN … #define NHMEX_M_PMON_ADDR_MATCH_MASK … #define NHMEX_M_PMON_ADDR_MASK_MASK … #define NHMEX_M_PMON_ADDR_MASK_SHIFT … #define NHMEX_M_PMON_CTL_EN … #define NHMEX_M_PMON_CTL_PMI_EN … #define NHMEX_M_PMON_CTL_COUNT_MODE_SHIFT … #define NHMEX_M_PMON_CTL_COUNT_MODE_MASK … #define NHMEX_M_PMON_CTL_STORAGE_MODE_SHIFT … #define NHMEX_M_PMON_CTL_STORAGE_MODE_MASK … #define NHMEX_M_PMON_CTL_WRAP_MODE … #define NHMEX_M_PMON_CTL_FLAG_MODE … #define NHMEX_M_PMON_CTL_INC_SEL_SHIFT … #define NHMEX_M_PMON_CTL_INC_SEL_MASK … #define NHMEX_M_PMON_CTL_SET_FLAG_SEL_SHIFT … #define NHMEX_M_PMON_CTL_SET_FLAG_SEL_MASK … #define NHMEX_M_PMON_RAW_EVENT_MASK … #define NHMEX_M_PMON_ZDP_CTL_FVC_MASK … #define NHMEX_M_PMON_ZDP_CTL_FVC_EVENT_MASK(n) … #define WSMEX_M_PMON_ZDP_CTL_FVC_MASK … #define WSMEX_M_PMON_ZDP_CTL_FVC_EVENT_MASK(n) … /* * use the 9~13 bits to select event If the 7th bit is not set, * otherwise use the 19~21 bits to select event. */ #define MBOX_INC_SEL(x) … #define MBOX_SET_FLAG_SEL(x) … #define MBOX_INC_SEL_MASK … #define MBOX_SET_FLAG_SEL_MASK … #define MBOX_INC_SEL_EXTAR_REG(c, r) … #define MBOX_SET_FLAG_SEL_EXTRA_REG(c, r) … /* NHM-EX Rbox */ #define NHMEX_R_MSR_GLOBAL_CTL … #define NHMEX_R_MSR_PMON_CTL0 … #define NHMEX_R_MSR_PMON_CNT0 … #define NHMEX_R_MSR_OFFSET … #define NHMEX_R_MSR_PORTN_QLX_CFG(n) … #define NHMEX_R_MSR_PORTN_IPERF_CFG0(n) … #define NHMEX_R_MSR_PORTN_IPERF_CFG1(n) … #define NHMEX_R_MSR_PORTN_XBR_OFFSET(n) … #define NHMEX_R_MSR_PORTN_XBR_SET1_MM_CFG(n) … #define NHMEX_R_MSR_PORTN_XBR_SET1_MATCH(n) … #define NHMEX_R_MSR_PORTN_XBR_SET1_MASK(n) … #define NHMEX_R_MSR_PORTN_XBR_SET2_MM_CFG(n) … #define NHMEX_R_MSR_PORTN_XBR_SET2_MATCH(n) … #define NHMEX_R_MSR_PORTN_XBR_SET2_MASK(n) … #define NHMEX_R_PMON_CTL_EN … #define NHMEX_R_PMON_CTL_EV_SEL_SHIFT … #define NHMEX_R_PMON_CTL_EV_SEL_MASK … #define NHMEX_R_PMON_CTL_PMI_EN … #define NHMEX_R_PMON_RAW_EVENT_MASK … /* NHM-EX Wbox */ #define NHMEX_W_MSR_GLOBAL_CTL … #define NHMEX_W_MSR_PMON_CNT0 … #define NHMEX_W_MSR_PMON_EVT_SEL0 … #define NHMEX_W_MSR_PMON_FIXED_CTR … #define NHMEX_W_MSR_PMON_FIXED_CTL … #define NHMEX_W_PMON_GLOBAL_FIXED_EN … #define __BITS_VALUE(x, i, n) … DEFINE_UNCORE_FORMAT_ATTR(…); DEFINE_UNCORE_FORMAT_ATTR(…); DEFINE_UNCORE_FORMAT_ATTR(…); DEFINE_UNCORE_FORMAT_ATTR(…); DEFINE_UNCORE_FORMAT_ATTR(…); DEFINE_UNCORE_FORMAT_ATTR(…); DEFINE_UNCORE_FORMAT_ATTR(…); DEFINE_UNCORE_FORMAT_ATTR(…); DEFINE_UNCORE_FORMAT_ATTR(…); static void nhmex_uncore_msr_init_box(struct intel_uncore_box *box) { … } static void nhmex_uncore_msr_exit_box(struct intel_uncore_box *box) { … } static void nhmex_uncore_msr_disable_box(struct intel_uncore_box *box) { … } static void nhmex_uncore_msr_enable_box(struct intel_uncore_box *box) { … } static void nhmex_uncore_msr_disable_event(struct intel_uncore_box *box, struct perf_event *event) { … } static void nhmex_uncore_msr_enable_event(struct intel_uncore_box *box, struct perf_event *event) { … } #define NHMEX_UNCORE_OPS_COMMON_INIT() … static struct intel_uncore_ops nhmex_uncore_ops = …; static struct attribute *nhmex_uncore_ubox_formats_attr[] = …; static const struct attribute_group nhmex_uncore_ubox_format_group = …; static struct intel_uncore_type nhmex_uncore_ubox = …; static struct attribute *nhmex_uncore_cbox_formats_attr[] = …; static const struct attribute_group nhmex_uncore_cbox_format_group = …; /* msr offset for each instance of cbox */ static u64 nhmex_cbox_msr_offsets[] = …; static struct intel_uncore_type nhmex_uncore_cbox = …; static struct uncore_event_desc nhmex_uncore_wbox_events[] = …; static struct intel_uncore_type nhmex_uncore_wbox = …; static int nhmex_bbox_hw_config(struct intel_uncore_box *box, struct perf_event *event) { … } static void nhmex_bbox_msr_enable_event(struct intel_uncore_box *box, struct perf_event *event) { … } /* * The Bbox has 4 counters, but each counter monitors different events. * Use bits 6-7 in the event config to select counter. */ static struct event_constraint nhmex_uncore_bbox_constraints[] = …; static struct attribute *nhmex_uncore_bbox_formats_attr[] = …; static const struct attribute_group nhmex_uncore_bbox_format_group = …; static struct intel_uncore_ops nhmex_uncore_bbox_ops = …; static struct intel_uncore_type nhmex_uncore_bbox = …; static int nhmex_sbox_hw_config(struct intel_uncore_box *box, struct perf_event *event) { … } static void nhmex_sbox_msr_enable_event(struct intel_uncore_box *box, struct perf_event *event) { … } static struct attribute *nhmex_uncore_sbox_formats_attr[] = …; static const struct attribute_group nhmex_uncore_sbox_format_group = …; static struct intel_uncore_ops nhmex_uncore_sbox_ops = …; static struct intel_uncore_type nhmex_uncore_sbox = …; enum { … }; static struct extra_reg nhmex_uncore_mbox_extra_regs[] = …; /* Nehalem-EX or Westmere-EX ? */ static bool uncore_nhmex; static bool nhmex_mbox_get_shared_reg(struct intel_uncore_box *box, int idx, u64 config) { … } static void nhmex_mbox_put_shared_reg(struct intel_uncore_box *box, int idx) { … } static u64 nhmex_mbox_alter_er(struct perf_event *event, int new_idx, bool modify) { … } static struct event_constraint * nhmex_mbox_get_constraint(struct intel_uncore_box *box, struct perf_event *event) { … } static void nhmex_mbox_put_constraint(struct intel_uncore_box *box, struct perf_event *event) { … } static int nhmex_mbox_extra_reg_idx(struct extra_reg *er) { … } static int nhmex_mbox_hw_config(struct intel_uncore_box *box, struct perf_event *event) { … } static u64 nhmex_mbox_shared_reg_config(struct intel_uncore_box *box, int idx) { … } static void nhmex_mbox_msr_enable_event(struct intel_uncore_box *box, struct perf_event *event) { … } DEFINE_UNCORE_FORMAT_ATTR(…); DEFINE_UNCORE_FORMAT_ATTR(…); DEFINE_UNCORE_FORMAT_ATTR(…); DEFINE_UNCORE_FORMAT_ATTR(…); DEFINE_UNCORE_FORMAT_ATTR(…); DEFINE_UNCORE_FORMAT_ATTR(…); DEFINE_UNCORE_FORMAT_ATTR(…); DEFINE_UNCORE_FORMAT_ATTR(…); DEFINE_UNCORE_FORMAT_ATTR(…); DEFINE_UNCORE_FORMAT_ATTR(…); DEFINE_UNCORE_FORMAT_ATTR(…); DEFINE_UNCORE_FORMAT_ATTR(…); DEFINE_UNCORE_FORMAT_ATTR(…); DEFINE_UNCORE_FORMAT_ATTR(…); DEFINE_UNCORE_FORMAT_ATTR(…); DEFINE_UNCORE_FORMAT_ATTR(…); static struct attribute *nhmex_uncore_mbox_formats_attr[] = …; static const struct attribute_group nhmex_uncore_mbox_format_group = …; static struct uncore_event_desc nhmex_uncore_mbox_events[] = …; static struct uncore_event_desc wsmex_uncore_mbox_events[] = …; static struct intel_uncore_ops nhmex_uncore_mbox_ops = …; static struct intel_uncore_type nhmex_uncore_mbox = …; static void nhmex_rbox_alter_er(struct intel_uncore_box *box, struct perf_event *event) { … } /* * Each rbox has 4 event set which monitor PQI port 0~3 or 4~7. * An event set consists of 6 events, the 3rd and 4th events in * an event set use the same extra register. So an event set uses * 5 extra registers. */ static struct event_constraint * nhmex_rbox_get_constraint(struct intel_uncore_box *box, struct perf_event *event) { … } static void nhmex_rbox_put_constraint(struct intel_uncore_box *box, struct perf_event *event) { … } static int nhmex_rbox_hw_config(struct intel_uncore_box *box, struct perf_event *event) { … } static void nhmex_rbox_msr_enable_event(struct intel_uncore_box *box, struct perf_event *event) { … } DEFINE_UNCORE_FORMAT_ATTR(…); DEFINE_UNCORE_FORMAT_ATTR(…); DEFINE_UNCORE_FORMAT_ATTR(…); DEFINE_UNCORE_FORMAT_ATTR(…); DEFINE_UNCORE_FORMAT_ATTR(…); static struct attribute *nhmex_uncore_rbox_formats_attr[] = …; static const struct attribute_group nhmex_uncore_rbox_format_group = …; static struct uncore_event_desc nhmex_uncore_rbox_events[] = …; static struct intel_uncore_ops nhmex_uncore_rbox_ops = …; static struct intel_uncore_type nhmex_uncore_rbox = …; static struct intel_uncore_type *nhmex_msr_uncores[] = …; void nhmex_uncore_cpu_init(void) { … } /* end of Nehalem-EX uncore support */
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