linux/drivers/clk/x86/clk-cgu.h

/* SPDX-License-Identifier: GPL-2.0 */
/*
 * Copyright (C) 2020-2022 MaxLinear, Inc.
 * Copyright (C) 2020 Intel Corporation.
 * Zhu Yixin <[email protected]>
 * Rahul Tanwar <[email protected]>
 */

#ifndef __CLK_CGU_H
#define __CLK_CGU_H

#include <linux/regmap.h>

struct lgm_clk_mux { … };

struct lgm_clk_divider { … };

struct lgm_clk_ddiv { … };

struct lgm_clk_gate { … };

enum lgm_clk_type { … };

/**
 * struct lgm_clk_provider
 * @membase: IO mem base address for CGU.
 * @np: device node
 * @dev: device
 * @clk_data: array of hw clocks and clk number.
 */
struct lgm_clk_provider { … };

enum pll_type { … };

struct lgm_clk_pll { … };

/**
 * struct lgm_pll_clk_data
 * @id: platform specific id of the clock.
 * @name: name of this pll clock.
 * @parent_data: parent clock data.
 * @num_parents: number of parents.
 * @flags: optional flags for basic clock.
 * @type: platform type of pll.
 * @reg: offset of the register.
 */
struct lgm_pll_clk_data { … };

#define LGM_PLL(_id, _name, _pdata, _flags,		\
		_reg, _type) …

struct lgm_clk_ddiv_data { … };

#define LGM_DDIV(_id, _name, _pname, _flags, _reg,		\
		 _shft0, _wdth0, _shft1, _wdth1,		\
		 _shft_gate, _wdth_gate, _xshft, _df) …

struct lgm_clk_branch { … };

/* clock flags definition */
#define CLOCK_FLAG_VAL_INIT …
#define MUX_CLK_SW …
#define GATE_CLK_HW …
#define DIV_CLK_NO_MASK …

#define LGM_MUX(_id, _name, _pdata, _f, _reg,		\
		_shift, _width, _cf, _v) …

#define LGM_DIV(_id, _name, _pname, _f, _reg, _shift, _width,	\
		_shift_gate, _width_gate, _cf, _v, _dtable) …

#define LGM_GATE(_id, _name, _pname, _f, _reg,			\
		 _shift, _cf, _v) …

#define LGM_FIXED(_id, _name, _pname, _f, _reg,			\
		  _shift, _width, _cf, _freq, _v) …

#define LGM_FIXED_FACTOR(_id, _name, _pname, _f, _reg,		\
			 _shift, _width, _cf, _v, _m, _d) …

static inline void lgm_set_clk_val(struct regmap *membase, u32 reg,
				   u8 shift, u8 width, u32 set_val)
{ … }

static inline u32 lgm_get_clk_val(struct regmap *membase, u32 reg,
				  u8 shift, u8 width)
{ … }



int lgm_clk_register_branches(struct lgm_clk_provider *ctx,
			      const struct lgm_clk_branch *list,
			      unsigned int nr_clk);
int lgm_clk_register_plls(struct lgm_clk_provider *ctx,
			  const struct lgm_pll_clk_data *list,
			  unsigned int nr_clk);
int lgm_clk_register_ddiv(struct lgm_clk_provider *ctx,
			  const struct lgm_clk_ddiv_data *list,
			  unsigned int nr_clk);
#endif	/* __CLK_CGU_H */