linux/drivers/clk/x86/clk-cgu-pll.c

// SPDX-License-Identifier: GPL-2.0
/*
 * Copyright (C) 2020-2022 MaxLinear, Inc.
 * Copyright (C) 2020 Intel Corporation.
 * Zhu Yixin <[email protected]>
 * Rahul Tanwar <[email protected]>
 */

#include <linux/clk-provider.h>
#include <linux/delay.h>
#include <linux/device.h>
#include <linux/iopoll.h>
#include <linux/of.h>

#include "clk-cgu.h"

#define to_lgm_clk_pll(_hw) …
#define PLL_REF_DIV(x) …

/*
 * Calculate formula:
 * rate = (prate * mult + (prate * frac) / frac_div) / div
 */
static unsigned long
lgm_pll_calc_rate(unsigned long prate, unsigned int mult,
		  unsigned int div, unsigned int frac, unsigned int frac_div)
{ … }

static unsigned long lgm_pll_recalc_rate(struct clk_hw *hw, unsigned long prate)
{ … }

static int lgm_pll_is_enabled(struct clk_hw *hw)
{ … }

static int lgm_pll_enable(struct clk_hw *hw)
{ … }

static void lgm_pll_disable(struct clk_hw *hw)
{ … }

static const struct clk_ops lgm_pll_ops = …;

static struct clk_hw *
lgm_clk_register_pll(struct lgm_clk_provider *ctx,
		     const struct lgm_pll_clk_data *list)
{ … }

int lgm_clk_register_plls(struct lgm_clk_provider *ctx,
			  const struct lgm_pll_clk_data *list,
			  unsigned int nr_clk)
{ … }