linux/drivers/clk/x86/clk-cgu.c

// SPDX-License-Identifier: GPL-2.0
/*
 * Copyright (C) 2020-2022 MaxLinear, Inc.
 * Copyright (C) 2020 Intel Corporation.
 * Zhu Yixin <[email protected]>
 * Rahul Tanwar <[email protected]>
 */
#include <linux/clk-provider.h>
#include <linux/device.h>
#include <linux/of.h>

#include "clk-cgu.h"

#define GATE_HW_REG_STAT(reg) …
#define GATE_HW_REG_EN(reg) …
#define GATE_HW_REG_DIS(reg) …
#define MAX_DDIV_REG …
#define MAX_DIVIDER_VAL …

#define to_lgm_clk_mux(_hw) …
#define to_lgm_clk_divider(_hw) …
#define to_lgm_clk_gate(_hw) …
#define to_lgm_clk_ddiv(_hw) …

static struct clk_hw *lgm_clk_register_fixed(struct lgm_clk_provider *ctx,
					     const struct lgm_clk_branch *list)
{ … }

static u8 lgm_clk_mux_get_parent(struct clk_hw *hw)
{ … }

static int lgm_clk_mux_set_parent(struct clk_hw *hw, u8 index)
{ … }

static int lgm_clk_mux_determine_rate(struct clk_hw *hw,
				      struct clk_rate_request *req)
{ … }

static const struct clk_ops lgm_clk_mux_ops = …;

static struct clk_hw *
lgm_clk_register_mux(struct lgm_clk_provider *ctx,
		     const struct lgm_clk_branch *list)
{ … }

static unsigned long
lgm_clk_divider_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
{ … }

static long
lgm_clk_divider_round_rate(struct clk_hw *hw, unsigned long rate,
			   unsigned long *prate)
{ … }

static int
lgm_clk_divider_set_rate(struct clk_hw *hw, unsigned long rate,
			 unsigned long prate)
{ … }

static int lgm_clk_divider_enable_disable(struct clk_hw *hw, int enable)
{ … }

static int lgm_clk_divider_enable(struct clk_hw *hw)
{ … }

static void lgm_clk_divider_disable(struct clk_hw *hw)
{ … }

static const struct clk_ops lgm_clk_divider_ops = …;

static struct clk_hw *
lgm_clk_register_divider(struct lgm_clk_provider *ctx,
			 const struct lgm_clk_branch *list)
{ … }

static struct clk_hw *
lgm_clk_register_fixed_factor(struct lgm_clk_provider *ctx,
			      const struct lgm_clk_branch *list)
{ … }

static int lgm_clk_gate_enable(struct clk_hw *hw)
{ … }

static void lgm_clk_gate_disable(struct clk_hw *hw)
{ … }

static int lgm_clk_gate_is_enabled(struct clk_hw *hw)
{ … }

static const struct clk_ops lgm_clk_gate_ops = …;

static struct clk_hw *
lgm_clk_register_gate(struct lgm_clk_provider *ctx,
		      const struct lgm_clk_branch *list)
{ … }

int lgm_clk_register_branches(struct lgm_clk_provider *ctx,
			      const struct lgm_clk_branch *list,
			      unsigned int nr_clk)
{ … }

static unsigned long
lgm_clk_ddiv_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
{ … }

static int lgm_clk_ddiv_enable(struct clk_hw *hw)
{ … }

static void lgm_clk_ddiv_disable(struct clk_hw *hw)
{ … }

static int
lgm_clk_get_ddiv_val(u32 div, u32 *ddiv1, u32 *ddiv2)
{ … }

static int
lgm_clk_ddiv_set_rate(struct clk_hw *hw, unsigned long rate,
		      unsigned long prate)
{ … }

static long
lgm_clk_ddiv_round_rate(struct clk_hw *hw, unsigned long rate,
			unsigned long *prate)
{ … }

static const struct clk_ops lgm_clk_ddiv_ops = …;

int lgm_clk_register_ddiv(struct lgm_clk_provider *ctx,
			  const struct lgm_clk_ddiv_data *list,
			  unsigned int nr_clk)
{ … }