// SPDX-License-Identifier: GPL-2.0 /* * Xilinx 'Clocking Wizard' driver * * Copyright (C) 2013 - 2021 Xilinx * * Sören Brinkmann <[email protected]> * */ #include <linux/bitfield.h> #include <linux/platform_device.h> #include <linux/clk.h> #include <linux/clk-provider.h> #include <linux/slab.h> #include <linux/io.h> #include <linux/of.h> #include <linux/math64.h> #include <linux/module.h> #include <linux/err.h> #include <linux/iopoll.h> #define WZRD_NUM_OUTPUTS … #define WZRD_ACLK_MAX_FREQ … #define WZRD_CLK_CFG_REG(v, n) … #define WZRD_CLKOUT0_FRAC_EN … #define WZRD_CLKFBOUT_1 … #define WZRD_CLKFBOUT_2 … #define WZRD_CLKOUT0_1 … #define WZRD_CLKOUT0_2 … #define WZRD_DESKEW_2 … #define WZRD_DIVCLK … #define WZRD_CLKFBOUT_4 … #define WZRD_CLKFBOUT_3 … #define WZRD_DUTY_CYCLE … #define WZRD_O_DIV … #define WZRD_CLKFBOUT_FRAC_EN … #define WZRD_CLKFBOUT_PREDIV2 … #define WZRD_MULT_PREDIV2 … #define WZRD_CLKFBOUT_EDGE … #define WZRD_P5EN … #define WZRD_P5EN_SHIFT … #define WZRD_P5FEDGE … #define WZRD_DIVCLK_EDGE … #define WZRD_P5FEDGE_SHIFT … #define WZRD_CLKOUT0_PREDIV2 … #define WZRD_EDGE_SHIFT … #define WZRD_CLKFBOUT_MULT_SHIFT … #define WZRD_CLKFBOUT_MULT_MASK … #define WZRD_CLKFBOUT_L_SHIFT … #define WZRD_CLKFBOUT_H_SHIFT … #define WZRD_CLKFBOUT_L_MASK … #define WZRD_CLKFBOUT_H_MASK … #define WZRD_CLKFBOUT_FRAC_SHIFT … #define WZRD_CLKFBOUT_FRAC_MASK … #define WZRD_VERSAL_FRAC_MASK … #define WZRD_DIVCLK_DIVIDE_SHIFT … #define WZRD_DIVCLK_DIVIDE_MASK … #define WZRD_CLKOUT_DIVIDE_SHIFT … #define WZRD_CLKOUT_DIVIDE_WIDTH … #define WZRD_CLKOUT_DIVIDE_MASK … #define WZRD_CLKOUT_FRAC_SHIFT … #define WZRD_CLKOUT_FRAC_MASK … #define WZRD_CLKOUT0_FRAC_MASK … #define WZRD_DR_MAX_INT_DIV_VALUE … #define WZRD_DR_STATUS_REG_OFFSET … #define WZRD_DR_LOCK_BIT_MASK … #define WZRD_DR_INIT_REG_OFFSET … #define WZRD_DR_INIT_VERSAL_OFFSET … #define WZRD_DR_DIV_TO_PHASE_OFFSET … #define WZRD_DR_BEGIN_DYNA_RECONF … #define WZRD_DR_BEGIN_DYNA_RECONF_5_2 … #define WZRD_DR_BEGIN_DYNA_RECONF1_5_2 … #define WZRD_USEC_POLL … #define WZRD_TIMEOUT_POLL … #define WZRD_FRAC_GRADIENT … #define PREDIV2_MULT … /* Divider limits, from UG572 Table 3-4 for Ultrascale+ */ #define DIV_O … #define DIV_ALL … #define WZRD_M_MIN … #define WZRD_M_MAX … #define WZRD_D_MIN … #define WZRD_D_MAX … #define WZRD_VCO_MIN … #define WZRD_VCO_MAX … #define WZRD_O_MIN … #define WZRD_O_MAX … #define VER_WZRD_M_MIN … #define VER_WZRD_M_MAX … #define VER_WZRD_D_MIN … #define VER_WZRD_D_MAX … #define VER_WZRD_VCO_MIN … #define VER_WZRD_VCO_MAX … #define VER_WZRD_O_MIN … #define VER_WZRD_O_MAX … #define WZRD_MIN_ERR … #define WZRD_FRAC_POINTS … /* Get the mask from width */ #define div_mask(width) … /* Extract divider instance from clock hardware instance */ #define to_clk_wzrd_divider(_hw) … enum clk_wzrd_int_clks { … }; /** * struct clk_wzrd - Clock wizard private data structure * * @clk_data: Clock data * @nb: Notifier block * @base: Memory base * @clk_in1: Handle to input clock 'clk_in1' * @axi_clk: Handle to input clock 's_axi_aclk' * @clks_internal: Internal clocks * @clkout: Output clocks * @speed_grade: Speed grade of the device * @suspended: Flag indicating power state of the device */ struct clk_wzrd { … }; /** * struct clk_wzrd_divider - clock divider specific to clk_wzrd * * @hw: handle between common and hardware-specific interfaces * @base: base address of register containing the divider * @offset: offset address of register containing the divider * @shift: shift to the divider bit field * @width: width of the divider bit field * @flags: clk_wzrd divider flags * @table: array of value/divider pairs, last entry should have div = 0 * @m: value of the multiplier * @d: value of the common divider * @o: value of the leaf divider * @lock: register lock */ struct clk_wzrd_divider { … }; struct versal_clk_data { … }; #define to_clk_wzrd(_nb) … /* maximum frequencies for input/output clocks per speed grade */ static const unsigned long clk_wzrd_max_freq[] = …; /* spin lock variable for clk_wzrd */ static DEFINE_SPINLOCK(clkwzrd_lock); static unsigned long clk_wzrd_recalc_rate_ver(struct clk_hw *hw, unsigned long parent_rate) { … } static unsigned long clk_wzrd_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) { … } static int clk_wzrd_ver_dynamic_reconfig(struct clk_hw *hw, unsigned long rate, unsigned long parent_rate) { … } static int clk_wzrd_dynamic_reconfig(struct clk_hw *hw, unsigned long rate, unsigned long parent_rate) { … } static long clk_wzrd_round_rate(struct clk_hw *hw, unsigned long rate, unsigned long *prate) { … } static int clk_wzrd_get_divisors_ver(struct clk_hw *hw, unsigned long rate, unsigned long parent_rate) { … } static int clk_wzrd_get_divisors(struct clk_hw *hw, unsigned long rate, unsigned long parent_rate) { … } static int clk_wzrd_reconfig(struct clk_wzrd_divider *divider, void __iomem *div_addr) { … } static int clk_wzrd_dynamic_ver_all_nolock(struct clk_hw *hw, unsigned long rate, unsigned long parent_rate) { … } static int clk_wzrd_dynamic_all_nolock(struct clk_hw *hw, unsigned long rate, unsigned long parent_rate) { … } static int clk_wzrd_dynamic_all(struct clk_hw *hw, unsigned long rate, unsigned long parent_rate) { … } static int clk_wzrd_dynamic_all_ver(struct clk_hw *hw, unsigned long rate, unsigned long parent_rate) { … } static unsigned long clk_wzrd_recalc_rate_all(struct clk_hw *hw, unsigned long parent_rate) { … } static unsigned long clk_wzrd_recalc_rate_all_ver(struct clk_hw *hw, unsigned long parent_rate) { … } static long clk_wzrd_round_rate_all(struct clk_hw *hw, unsigned long rate, unsigned long *prate) { … } static const struct clk_ops clk_wzrd_ver_divider_ops = …; static const struct clk_ops clk_wzrd_ver_div_all_ops = …; static const struct clk_ops clk_wzrd_clk_divider_ops = …; static const struct clk_ops clk_wzrd_clk_div_all_ops = …; static unsigned long clk_wzrd_recalc_ratef(struct clk_hw *hw, unsigned long parent_rate) { … } static int clk_wzrd_dynamic_reconfig_f(struct clk_hw *hw, unsigned long rate, unsigned long parent_rate) { … } static long clk_wzrd_round_rate_f(struct clk_hw *hw, unsigned long rate, unsigned long *prate) { … } static const struct clk_ops clk_wzrd_clk_divider_ops_f = …; static struct clk *clk_wzrd_register_divf(struct device *dev, const char *name, const char *parent_name, unsigned long flags, void __iomem *base, u16 offset, u8 shift, u8 width, u8 clk_divider_flags, u32 div_type, spinlock_t *lock) { … } static struct clk *clk_wzrd_ver_register_divider(struct device *dev, const char *name, const char *parent_name, unsigned long flags, void __iomem *base, u16 offset, u8 shift, u8 width, u8 clk_divider_flags, u32 div_type, spinlock_t *lock) { … } static struct clk *clk_wzrd_register_divider(struct device *dev, const char *name, const char *parent_name, unsigned long flags, void __iomem *base, u16 offset, u8 shift, u8 width, u8 clk_divider_flags, u32 div_type, spinlock_t *lock) { … } static int clk_wzrd_clk_notifier(struct notifier_block *nb, unsigned long event, void *data) { … } static int __maybe_unused clk_wzrd_suspend(struct device *dev) { … } static int __maybe_unused clk_wzrd_resume(struct device *dev) { … } static SIMPLE_DEV_PM_OPS(clk_wzrd_dev_pm_ops, clk_wzrd_suspend, clk_wzrd_resume); static const struct versal_clk_data versal_data = …; static int clk_wzrd_probe(struct platform_device *pdev) { … } static void clk_wzrd_remove(struct platform_device *pdev) { … } static const struct of_device_id clk_wzrd_ids[] = …; MODULE_DEVICE_TABLE(of, clk_wzrd_ids); static struct platform_driver clk_wzrd_driver = …; module_platform_driver(…) …; MODULE_LICENSE(…) …; MODULE_AUTHOR(…) …; MODULE_DESCRIPTION(…) …;
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