clk-divider.c | Explore in Territory

// SPDX-License-Identifier: GPL-2.0
/*
 * Copyright (C) 2011 Sascha Hauer, Pengutronix <[email protected]>
 * Copyright (C) 2011 Richard Zhao, Linaro <[email protected]>
 * Copyright (C) 2011-2012 Mike Turquette, Linaro Ltd <[email protected]>
 *
 * Adjustable divider clock implementation
 */

#include <linux/clk-provider.h>
#include <linux/device.h>
#include <linux/module.h>
#include <linux/slab.h>
#include <linux/io.h>
#include <linux/err.h>
#include <linux/string.h>
#include <linux/log2.h>

/*
 * DOC: basic adjustable divider clock that cannot gate
 *
 * Traits of this clock:
 * prepare - clk_prepare only ensures that parents are prepared
 * enable - clk_enable only ensures that parents are enabled
 * rate - rate is adjustable.  clk->rate = ceiling(parent->rate / divisor)
 * parent - fixed parent.  No clk_set_parent support
 */

static inline u32 clk_div_readl(struct clk_divider *divider)
{ … }

static inline void clk_div_writel(struct clk_divider *divider, u32 val)
{ … }

static unsigned int _get_table_maxdiv(const struct clk_div_table *table,
				      u8 width)
{ … }

static unsigned int _get_table_mindiv(const struct clk_div_table *table)
{ … }

static unsigned int _get_maxdiv(const struct clk_div_table *table, u8 width,
				unsigned long flags)
{ … }

static unsigned int _get_table_div(const struct clk_div_table *table,
							unsigned int val)
{ … }

static unsigned int _get_div(const struct clk_div_table *table,
			     unsigned int val, unsigned long flags, u8 width)
{ … }

static unsigned int _get_table_val(const struct clk_div_table *table,
							unsigned int div)
{ … }

static unsigned int _get_val(const struct clk_div_table *table,
			     unsigned int div, unsigned long flags, u8 width)
{ … }

unsigned long divider_recalc_rate(struct clk_hw *hw, unsigned long parent_rate,
				  unsigned int val,
				  const struct clk_div_table *table,
				  unsigned long flags, unsigned long width)
{ … }
EXPORT_SYMBOL_GPL(…);

static unsigned long clk_divider_recalc_rate(struct clk_hw *hw,
		unsigned long parent_rate)
{ … }

static bool _is_valid_table_div(const struct clk_div_table *table,
							 unsigned int div)
{ … }

static bool _is_valid_div(const struct clk_div_table *table, unsigned int div,
			  unsigned long flags)
{ … }

static int _round_up_table(const struct clk_div_table *table, int div)
{ … }

static int _round_down_table(const struct clk_div_table *table, int div)
{ … }

static int _div_round_up(const struct clk_div_table *table,
			 unsigned long parent_rate, unsigned long rate,
			 unsigned long flags)
{ … }

static int _div_round_closest(const struct clk_div_table *table,
			      unsigned long parent_rate, unsigned long rate,
			      unsigned long flags)
{ … }

static int _div_round(const struct clk_div_table *table,
		      unsigned long parent_rate, unsigned long rate,
		      unsigned long flags)
{ … }

static bool _is_best_div(unsigned long rate, unsigned long now,
			 unsigned long best, unsigned long flags)
{ … }

static int _next_div(const struct clk_div_table *table, int div,
		     unsigned long flags)
{ … }

static int clk_divider_bestdiv(struct clk_hw *hw, struct clk_hw *parent,
			       unsigned long rate,
			       unsigned long *best_parent_rate,
			       const struct clk_div_table *table, u8 width,
			       unsigned long flags)
{ … }

int divider_determine_rate(struct clk_hw *hw, struct clk_rate_request *req,
			   const struct clk_div_table *table, u8 width,
			   unsigned long flags)
{ … }
EXPORT_SYMBOL_GPL(…);

int divider_ro_determine_rate(struct clk_hw *hw, struct clk_rate_request *req,
			      const struct clk_div_table *table, u8 width,
			      unsigned long flags, unsigned int val)
{ … }
EXPORT_SYMBOL_GPL(…);

long divider_round_rate_parent(struct clk_hw *hw, struct clk_hw *parent,
			       unsigned long rate, unsigned long *prate,
			       const struct clk_div_table *table,
			       u8 width, unsigned long flags)
{ … }
EXPORT_SYMBOL_GPL(…);

long divider_ro_round_rate_parent(struct clk_hw *hw, struct clk_hw *parent,
				  unsigned long rate, unsigned long *prate,
				  const struct clk_div_table *table, u8 width,
				  unsigned long flags, unsigned int val)
{ … }
EXPORT_SYMBOL_GPL(…);

static long clk_divider_round_rate(struct clk_hw *hw, unsigned long rate,
				unsigned long *prate)
{ … }

static int clk_divider_determine_rate(struct clk_hw *hw,
				      struct clk_rate_request *req)
{ … }

int divider_get_val(unsigned long rate, unsigned long parent_rate,
		    const struct clk_div_table *table, u8 width,
		    unsigned long flags)
{ … }
EXPORT_SYMBOL_GPL(…);

static int clk_divider_set_rate(struct clk_hw *hw, unsigned long rate,
				unsigned long parent_rate)
{ … }

const struct clk_ops clk_divider_ops = …;
EXPORT_SYMBOL_GPL(…);

const struct clk_ops clk_divider_ro_ops = …;
EXPORT_SYMBOL_GPL(…);

struct clk_hw *__clk_hw_register_divider(struct device *dev,
		struct device_node *np, const char *name,
		const char *parent_name, const struct clk_hw *parent_hw,
		const struct clk_parent_data *parent_data, unsigned long flags,
		void __iomem *reg, u8 shift, u8 width, u8 clk_divider_flags,
		const struct clk_div_table *table, spinlock_t *lock)
{ … }
EXPORT_SYMBOL_GPL(…);

/**
 * clk_register_divider_table - register a table based divider clock with
 * the clock framework
 * @dev: device registering this clock
 * @name: name of this clock
 * @parent_name: name of clock's parent
 * @flags: framework-specific flags
 * @reg: register address to adjust divider
 * @shift: number of bits to shift the bitfield
 * @width: width of the bitfield
 * @clk_divider_flags: divider-specific flags for this clock
 * @table: array of divider/value pairs ending with a div set to 0
 * @lock: shared register lock for this clock
 */
struct clk *clk_register_divider_table(struct device *dev, const char *name,
		const char *parent_name, unsigned long flags,
		void __iomem *reg, u8 shift, u8 width,
		u8 clk_divider_flags, const struct clk_div_table *table,
		spinlock_t *lock)
{ … }
EXPORT_SYMBOL_GPL(…);

void clk_unregister_divider(struct clk *clk)
{ … }
EXPORT_SYMBOL_GPL(…);

/**
 * clk_hw_unregister_divider - unregister a clk divider
 * @hw: hardware-specific clock data to unregister
 */
void clk_hw_unregister_divider(struct clk_hw *hw)
{ … }
EXPORT_SYMBOL_GPL(…);

static void devm_clk_hw_release_divider(struct device *dev, void *res)
{ … }

struct clk_hw *__devm_clk_hw_register_divider(struct device *dev,
		struct device_node *np, const char *name,
		const char *parent_name, const struct clk_hw *parent_hw,
		const struct clk_parent_data *parent_data, unsigned long flags,
		void __iomem *reg, u8 shift, u8 width, u8 clk_divider_flags,
		const struct clk_div_table *table, spinlock_t *lock)
{ … }
EXPORT_SYMBOL_GPL(…);
linux/drivers/clk/clk-divider.c
