// SPDX-License-Identifier: GPL-2.0 /* * Copyright (C) 2020-2022 MaxLinear, Inc. * Copyright (C) 2020 Intel Corporation. * Zhu Yixin <[email protected]> * Rahul Tanwar <[email protected]> */ #include <linux/clk-provider.h> #include <linux/mfd/syscon.h> #include <linux/of.h> #include <linux/platform_device.h> #include <dt-bindings/clock/intel,lgm-clk.h> #include "clk-cgu.h" #define PLL_DIV_WIDTH … #define PLL_DDIV_WIDTH … /* Gate0 clock shift */ #define G_C55_SHIFT … #define G_QSPI_SHIFT … #define G_EIP197_SHIFT … #define G_VAULT130_SHIFT … #define G_TOE_SHIFT … #define G_SDXC_SHIFT … #define G_EMMC_SHIFT … #define G_SPIDBG_SHIFT … #define G_DMA3_SHIFT … /* Gate1 clock shift */ #define G_DMA0_SHIFT … #define G_LEDC0_SHIFT … #define G_LEDC1_SHIFT … #define G_I2S0_SHIFT … #define G_I2S1_SHIFT … #define G_EBU_SHIFT … #define G_PWM_SHIFT … #define G_I2C0_SHIFT … #define G_I2C1_SHIFT … #define G_I2C2_SHIFT … #define G_I2C3_SHIFT … #define G_SSC0_SHIFT … #define G_SSC1_SHIFT … #define G_SSC2_SHIFT … #define G_SSC3_SHIFT … #define G_GPTC0_SHIFT … #define G_GPTC1_SHIFT … #define G_GPTC2_SHIFT … #define G_GPTC3_SHIFT … #define G_ASC0_SHIFT … #define G_ASC1_SHIFT … #define G_ASC2_SHIFT … #define G_ASC3_SHIFT … #define G_PCM0_SHIFT … #define G_PCM1_SHIFT … #define G_PCM2_SHIFT … /* Gate2 clock shift */ #define G_PCIE10_SHIFT … #define G_PCIE11_SHIFT … #define G_PCIE30_SHIFT … #define G_PCIE31_SHIFT … #define G_PCIE20_SHIFT … #define G_PCIE21_SHIFT … #define G_PCIE40_SHIFT … #define G_PCIE41_SHIFT … #define G_XPCS0_SHIFT … #define G_XPCS1_SHIFT … #define G_XPCS2_SHIFT … #define G_XPCS3_SHIFT … #define G_SATA0_SHIFT … #define G_SATA1_SHIFT … #define G_SATA2_SHIFT … #define G_SATA3_SHIFT … /* Gate3 clock shift */ #define G_ARCEM4_SHIFT … #define G_IDMAR1_SHIFT … #define G_IDMAT0_SHIFT … #define G_IDMAT1_SHIFT … #define G_IDMAT2_SHIFT … #define G_PPV4_SHIFT … #define G_GSWIPO_SHIFT … #define G_CQEM_SHIFT … #define G_XPCS5_SHIFT … #define G_USB1_SHIFT … #define G_USB2_SHIFT … /* Register definition */ #define CGU_PLL0CZ_CFG0 … #define CGU_PLL0CM0_CFG0 … #define CGU_PLL0CM1_CFG0 … #define CGU_PLL0B_CFG0 … #define CGU_PLL1_CFG0 … #define CGU_PLL2_CFG0 … #define CGU_PLLPP_CFG0 … #define CGU_LJPLL3_CFG0 … #define CGU_LJPLL4_CFG0 … #define CGU_C55_PCMCR … #define CGU_PCMCR … #define CGU_IF_CLK1 … #define CGU_IF_CLK2 … #define CGU_GATE0 … #define CGU_GATE1 … #define CGU_GATE2 … #define CGU_GATE3 … #define PLL_DIV(x) … #define PLL_SSC(x) … #define CLK_NR_CLKS … /* * Below table defines the pair's of regval & effective dividers. * It's more efficient to provide an explicit table due to non-linear * relation between values. */ static const struct clk_div_table pll_div[] = …; static const struct clk_div_table dcl_div[] = …; static const struct clk_parent_data pll_p[] = …; static const struct clk_parent_data pllcm_p[] = …; static const struct clk_parent_data emmc_p[] = …; static const struct clk_parent_data sdxc_p[] = …; static const struct clk_parent_data pcm_p[] = …; static const struct clk_parent_data cbphy_p[] = …; static const struct lgm_pll_clk_data lgm_pll_clks[] = …; static const struct lgm_clk_branch lgm_branch_clks[] = …; static const struct lgm_clk_ddiv_data lgm_ddiv_clks[] = …; static int lgm_cgu_probe(struct platform_device *pdev) { … } static const struct of_device_id of_lgm_cgu_match[] = …; static struct platform_driver lgm_cgu_driver = …; builtin_platform_driver(…) …;
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