linux/drivers/clk/clk-axi-clkgen.c

// SPDX-License-Identifier: GPL-2.0-only
/*
 * AXI clkgen driver
 *
 * Copyright 2012-2013 Analog Devices Inc.
 *  Author: Lars-Peter Clausen <[email protected]>
 */

#include <linux/platform_device.h>
#include <linux/clk-provider.h>
#include <linux/slab.h>
#include <linux/io.h>
#include <linux/of.h>
#include <linux/module.h>
#include <linux/err.h>

#define AXI_CLKGEN_V2_REG_RESET …
#define AXI_CLKGEN_V2_REG_CLKSEL …
#define AXI_CLKGEN_V2_REG_DRP_CNTRL …
#define AXI_CLKGEN_V2_REG_DRP_STATUS …

#define AXI_CLKGEN_V2_RESET_MMCM_ENABLE …
#define AXI_CLKGEN_V2_RESET_ENABLE …

#define AXI_CLKGEN_V2_DRP_CNTRL_SEL …
#define AXI_CLKGEN_V2_DRP_CNTRL_READ …

#define AXI_CLKGEN_V2_DRP_STATUS_BUSY …

#define MMCM_REG_CLKOUT5_2 …
#define MMCM_REG_CLKOUT0_1 …
#define MMCM_REG_CLKOUT0_2 …
#define MMCM_REG_CLKOUT6_2 …
#define MMCM_REG_CLK_FB1 …
#define MMCM_REG_CLK_FB2 …
#define MMCM_REG_CLK_DIV …
#define MMCM_REG_LOCK1 …
#define MMCM_REG_LOCK2 …
#define MMCM_REG_LOCK3 …
#define MMCM_REG_POWER …
#define MMCM_REG_FILTER1 …
#define MMCM_REG_FILTER2 …

#define MMCM_CLKOUT_NOCOUNT …

#define MMCM_CLK_DIV_DIVIDE …
#define MMCM_CLK_DIV_NOCOUNT …

struct axi_clkgen_limits { … };

struct axi_clkgen { … };

static uint32_t axi_clkgen_lookup_filter(unsigned int m)
{ … }

static const uint32_t axi_clkgen_lock_table[] = …;

static uint32_t axi_clkgen_lookup_lock(unsigned int m)
{ … }

static const struct axi_clkgen_limits axi_clkgen_zynqmp_default_limits = …;

static const struct axi_clkgen_limits axi_clkgen_zynq_default_limits = …;

static void axi_clkgen_calc_params(const struct axi_clkgen_limits *limits,
	unsigned long fin, unsigned long fout,
	unsigned int *best_d, unsigned int *best_m, unsigned int *best_dout)
{ … }

struct axi_clkgen_div_params { … };

static void axi_clkgen_calc_clk_params(unsigned int divider,
	unsigned int frac_divider, struct axi_clkgen_div_params *params)
{ … }

static void axi_clkgen_write(struct axi_clkgen *axi_clkgen,
	unsigned int reg, unsigned int val)
{ … }

static void axi_clkgen_read(struct axi_clkgen *axi_clkgen,
	unsigned int reg, unsigned int *val)
{ … }

static int axi_clkgen_wait_non_busy(struct axi_clkgen *axi_clkgen)
{ … }

static int axi_clkgen_mmcm_read(struct axi_clkgen *axi_clkgen,
	unsigned int reg, unsigned int *val)
{ … }

static int axi_clkgen_mmcm_write(struct axi_clkgen *axi_clkgen,
	unsigned int reg, unsigned int val, unsigned int mask)
{ … }

static void axi_clkgen_mmcm_enable(struct axi_clkgen *axi_clkgen,
	bool enable)
{ … }

static struct axi_clkgen *clk_hw_to_axi_clkgen(struct clk_hw *clk_hw)
{ … }

static void axi_clkgen_set_div(struct axi_clkgen *axi_clkgen,
	unsigned int reg1, unsigned int reg2, unsigned int reg3,
	struct axi_clkgen_div_params *params)
{ … }

static int axi_clkgen_set_rate(struct clk_hw *clk_hw,
	unsigned long rate, unsigned long parent_rate)
{ … }

static int axi_clkgen_determine_rate(struct clk_hw *hw,
				     struct clk_rate_request *req)
{ … }

static unsigned int axi_clkgen_get_div(struct axi_clkgen *axi_clkgen,
	unsigned int reg1, unsigned int reg2)
{ … }

static unsigned long axi_clkgen_recalc_rate(struct clk_hw *clk_hw,
	unsigned long parent_rate)
{ … }

static int axi_clkgen_enable(struct clk_hw *clk_hw)
{ … }

static void axi_clkgen_disable(struct clk_hw *clk_hw)
{ … }

static int axi_clkgen_set_parent(struct clk_hw *clk_hw, u8 index)
{ … }

static u8 axi_clkgen_get_parent(struct clk_hw *clk_hw)
{ … }

static const struct clk_ops axi_clkgen_ops = …;

static int axi_clkgen_probe(struct platform_device *pdev)
{ … }

static const struct of_device_id axi_clkgen_ids[] = …;
MODULE_DEVICE_TABLE(of, axi_clkgen_ids);

static struct platform_driver axi_clkgen_driver = …;
module_platform_driver(…) …;

MODULE_LICENSE(…) …;
MODULE_AUTHOR(…) …;
MODULE_DESCRIPTION(…) …;