// SPDX-License-Identifier: GPL-2.0+ /* * Bitmain BM1880 SoC clock driver * * Copyright (c) 2019 Linaro Ltd. * Author: Manivannan Sadhasivam <[email protected]> */ #include <linux/clk-provider.h> #include <linux/io.h> #include <linux/kernel.h> #include <linux/mod_devicetable.h> #include <linux/module.h> #include <linux/platform_device.h> #include <linux/slab.h> #include <dt-bindings/clock/bm1880-clock.h> #define BM1880_CLK_MPLL_CTL … #define BM1880_CLK_SPLL_CTL … #define BM1880_CLK_FPLL_CTL … #define BM1880_CLK_DDRPLL_CTL … #define BM1880_CLK_ENABLE0 … #define BM1880_CLK_ENABLE1 … #define BM1880_CLK_SELECT … #define BM1880_CLK_DIV0 … #define BM1880_CLK_DIV1 … #define BM1880_CLK_DIV2 … #define BM1880_CLK_DIV3 … #define BM1880_CLK_DIV4 … #define BM1880_CLK_DIV5 … #define BM1880_CLK_DIV6 … #define BM1880_CLK_DIV7 … #define BM1880_CLK_DIV8 … #define BM1880_CLK_DIV9 … #define BM1880_CLK_DIV10 … #define BM1880_CLK_DIV11 … #define BM1880_CLK_DIV12 … #define BM1880_CLK_DIV13 … #define BM1880_CLK_DIV14 … #define BM1880_CLK_DIV15 … #define BM1880_CLK_DIV16 … #define BM1880_CLK_DIV17 … #define BM1880_CLK_DIV18 … #define BM1880_CLK_DIV19 … #define BM1880_CLK_DIV20 … #define BM1880_CLK_DIV21 … #define BM1880_CLK_DIV22 … #define BM1880_CLK_DIV23 … #define BM1880_CLK_DIV24 … #define BM1880_CLK_DIV25 … #define BM1880_CLK_DIV26 … #define BM1880_CLK_DIV27 … #define BM1880_CLK_DIV28 … #define to_bm1880_pll_clk(_hw) … #define to_bm1880_div_clk(_hw) … static DEFINE_SPINLOCK(bm1880_clk_lock); struct bm1880_clock_data { … }; struct bm1880_gate_clock { … }; struct bm1880_mux_clock { … }; struct bm1880_div_clock { … }; struct bm1880_div_hw_clock { … }; struct bm1880_composite_clock { … }; struct bm1880_pll_clock { … }; struct bm1880_pll_hw_clock { … }; static const struct clk_ops bm1880_pll_ops; static const struct clk_ops bm1880_clk_div_ops; #define GATE_DIV(_id, _name, _parent, _gate_reg, _gate_shift, _div_reg, \ _div_shift, _div_width, _div_initval, _table, \ _flags) … #define GATE_MUX(_id, _name, _parents, _gate_reg, _gate_shift, \ _mux_reg, _mux_shift, _flags) … #define CLK_PLL(_id, _name, _parent, _reg, _flags) … #define CLK_DIV(_id, _name, _parent, _reg, _shift, _width, _initval, \ _table, _flags) … static struct clk_parent_data bm1880_pll_parent[] = …; /* * All PLL clocks are marked as CRITICAL, hence they are very crucial * for the functioning of the SoC */ static struct bm1880_pll_hw_clock bm1880_pll_clks[] = …; /* * Clocks marked as CRITICAL are needed for the proper functioning * of the SoC. */ static const struct bm1880_gate_clock bm1880_gate_clks[] = …; static const char * const clk_a53_parents[] = …; static const char * const clk_rv_parents[] = …; static const char * const clk_axi1_parents[] = …; static const char * const clk_axi6_parents[] = …; static const struct bm1880_mux_clock bm1880_mux_clks[] = …; static const struct clk_div_table bm1880_div_table_0[] = …; static const struct clk_div_table bm1880_div_table_1[] = …; static const struct clk_div_table bm1880_div_table_2[] = …; static const struct clk_div_table bm1880_div_table_3[] = …; static const struct clk_div_table bm1880_div_table_4[] = …; /* * Clocks marked as CRITICAL are needed for the proper functioning * of the SoC. */ static struct bm1880_div_hw_clock bm1880_div_clks[] = …; /* * Clocks marked as CRITICAL are all needed for the proper functioning * of the SoC. */ static struct bm1880_composite_clock bm1880_composite_clks[] = …; static unsigned long bm1880_pll_rate_calc(u32 regval, unsigned long parent_rate) { … } static unsigned long bm1880_pll_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) { … } static const struct clk_ops bm1880_pll_ops = …; static struct clk_hw *bm1880_clk_register_pll(struct bm1880_pll_hw_clock *pll_clk, void __iomem *sys_base) { … } static int bm1880_clk_register_plls(struct bm1880_pll_hw_clock *clks, int num_clks, struct bm1880_clock_data *data) { … } static int bm1880_clk_register_mux(const struct bm1880_mux_clock *clks, int num_clks, struct bm1880_clock_data *data) { … } static unsigned long bm1880_clk_div_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) { … } static long bm1880_clk_div_round_rate(struct clk_hw *hw, unsigned long rate, unsigned long *prate) { … } static int bm1880_clk_div_set_rate(struct clk_hw *hw, unsigned long rate, unsigned long parent_rate) { … } static const struct clk_ops bm1880_clk_div_ops = …; static struct clk_hw *bm1880_clk_register_div(struct bm1880_div_hw_clock *div_clk, void __iomem *sys_base) { … } static int bm1880_clk_register_divs(struct bm1880_div_hw_clock *clks, int num_clks, struct bm1880_clock_data *data) { … } static int bm1880_clk_register_gate(const struct bm1880_gate_clock *clks, int num_clks, struct bm1880_clock_data *data) { … } static struct clk_hw *bm1880_clk_register_composite(struct bm1880_composite_clock *clks, void __iomem *sys_base) { … } static int bm1880_clk_register_composites(struct bm1880_composite_clock *clks, int num_clks, struct bm1880_clock_data *data) { … } static int bm1880_clk_probe(struct platform_device *pdev) { … } static const struct of_device_id bm1880_of_match[] = …; MODULE_DEVICE_TABLE(of, bm1880_of_match); static struct platform_driver bm1880_clk_driver = …; module_platform_driver(…) …; MODULE_AUTHOR(…) …; MODULE_DESCRIPTION(…) …;
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