linux/drivers/clk/clk-hsdk-pll.c

// SPDX-License-Identifier: GPL-2.0-only
/*
 * Synopsys HSDK SDP Generic PLL clock driver
 *
 * Copyright (C) 2017 Synopsys
 */

#include <linux/clk-provider.h>
#include <linux/delay.h>
#include <linux/device.h>
#include <linux/err.h>
#include <linux/io.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/platform_device.h>
#include <linux/slab.h>

#define CGU_PLL_CTRL …
#define CGU_PLL_STATUS …
#define CGU_PLL_FMEAS …
#define CGU_PLL_MON …

#define CGU_PLL_CTRL_ODIV_SHIFT …
#define CGU_PLL_CTRL_IDIV_SHIFT …
#define CGU_PLL_CTRL_FBDIV_SHIFT …
#define CGU_PLL_CTRL_BAND_SHIFT …

#define CGU_PLL_CTRL_ODIV_MASK …
#define CGU_PLL_CTRL_IDIV_MASK …
#define CGU_PLL_CTRL_FBDIV_MASK …

#define CGU_PLL_CTRL_PD …
#define CGU_PLL_CTRL_BYPASS …

#define CGU_PLL_STATUS_LOCK …
#define CGU_PLL_STATUS_ERR …

#define HSDK_PLL_MAX_LOCK_TIME …

#define CGU_PLL_SOURCE_MAX …

#define CORE_IF_CLK_THRESHOLD_HZ …
#define CREG_CORE_IF_CLK_DIV_1 …
#define CREG_CORE_IF_CLK_DIV_2 …

struct hsdk_pll_cfg { … };

static const struct hsdk_pll_cfg asdt_pll_cfg[] = …;

static const struct hsdk_pll_cfg hdmi_pll_cfg[] = …;

struct hsdk_pll_clk { … };

struct hsdk_pll_devdata { … };

static int hsdk_pll_core_update_rate(struct hsdk_pll_clk *, unsigned long,
				     const struct hsdk_pll_cfg *);
static int hsdk_pll_comm_update_rate(struct hsdk_pll_clk *, unsigned long,
				     const struct hsdk_pll_cfg *);

static const struct hsdk_pll_devdata core_pll_devdata = …;

static const struct hsdk_pll_devdata sdt_pll_devdata = …;

static const struct hsdk_pll_devdata hdmi_pll_devdata = …;

static inline void hsdk_pll_write(struct hsdk_pll_clk *clk, u32 reg, u32 val)
{ … }

static inline u32 hsdk_pll_read(struct hsdk_pll_clk *clk, u32 reg)
{ … }

static inline void hsdk_pll_set_cfg(struct hsdk_pll_clk *clk,
				    const struct hsdk_pll_cfg *cfg)
{ … }

static inline bool hsdk_pll_is_locked(struct hsdk_pll_clk *clk)
{ … }

static inline bool hsdk_pll_is_err(struct hsdk_pll_clk *clk)
{ … }

static inline struct hsdk_pll_clk *to_hsdk_pll_clk(struct clk_hw *hw)
{ … }

static unsigned long hsdk_pll_recalc_rate(struct clk_hw *hw,
					  unsigned long parent_rate)
{ … }

static long hsdk_pll_round_rate(struct clk_hw *hw, unsigned long rate,
				unsigned long *prate)
{ … }

static int hsdk_pll_comm_update_rate(struct hsdk_pll_clk *clk,
				     unsigned long rate,
				     const struct hsdk_pll_cfg *cfg)
{ … }

static int hsdk_pll_core_update_rate(struct hsdk_pll_clk *clk,
				     unsigned long rate,
				     const struct hsdk_pll_cfg *cfg)
{ … }

static int hsdk_pll_set_rate(struct clk_hw *hw, unsigned long rate,
			     unsigned long parent_rate)
{ … }

static const struct clk_ops hsdk_pll_ops = …;

static int hsdk_pll_clk_probe(struct platform_device *pdev)
{ … }

static void __init of_hsdk_pll_clk_setup(struct device_node *node)
{ … }

/* Core PLL needed early for ARC cpus timers */
CLK_OF_DECLARE(hsdk_pll_clock, "snps,hsdk-core-pll-clock",
of_hsdk_pll_clk_setup);

static const struct of_device_id hsdk_pll_clk_id[] = …;

static struct platform_driver hsdk_pll_clk_driver = …;
builtin_platform_driver(…) …;