// SPDX-License-Identifier: GPL-2.0+ // Copyright IBM Corp #define pr_fmt(fmt) … #include <linux/mfd/syscon.h> #include <linux/of.h> #include <linux/of_address.h> #include <linux/platform_device.h> #include <linux/regmap.h> #include <linux/slab.h> #include <dt-bindings/clock/aspeed-clock.h> #include "clk-aspeed.h" #define ASPEED_NUM_CLKS … #define ASPEED_RESET2_OFFSET … #define ASPEED_RESET_CTRL … #define ASPEED_CLK_SELECTION … #define ASPEED_CLK_STOP_CTRL … #define ASPEED_MPLL_PARAM … #define ASPEED_HPLL_PARAM … #define AST2500_HPLL_BYPASS_EN … #define AST2400_HPLL_PROGRAMMED … #define AST2400_HPLL_BYPASS_EN … #define ASPEED_MISC_CTRL … #define UART_DIV13_EN … #define ASPEED_MAC_CLK_DLY … #define ASPEED_STRAP … #define CLKIN_25MHZ_EN … #define AST2400_CLK_SOURCE_SEL … #define ASPEED_CLK_SELECTION_2 … #define ASPEED_RESET_CTRL2 … /* Globally visible clocks */ static DEFINE_SPINLOCK(aspeed_clk_lock); /* Keeps track of all clocks */ static struct clk_hw_onecell_data *aspeed_clk_data; static void __iomem *scu_base; /* TODO: ask Aspeed about the actual parent data */ static const struct aspeed_gate_data aspeed_gates[] = …; static const char * const eclk_parent_names[] = …; static const struct clk_div_table ast2500_eclk_div_table[] = …; static const struct clk_div_table ast2500_mac_div_table[] = …; static const struct clk_div_table ast2400_div_table[] = …; static const struct clk_div_table ast2500_div_table[] = …; static struct clk_hw *aspeed_ast2400_calc_pll(const char *name, u32 val) { unsigned int mult, div; if (val & AST2400_HPLL_BYPASS_EN) { /* Pass through mode */ mult = div = 1; } else { /* F = 24Mhz * (2-OD) * [(N + 2) / (D + 1)] */ u32 n = (val >> 5) & 0x3f; u32 od = (val >> 4) & 0x1; u32 d = val & 0xf; mult = (2 - od) * (n + 2); div = d + 1; } return clk_hw_register_fixed_factor(NULL, name, "clkin", 0, mult, div); }; static struct clk_hw *aspeed_ast2500_calc_pll(const char *name, u32 val) { … } static const struct aspeed_clk_soc_data ast2500_data = …; static const struct aspeed_clk_soc_data ast2400_data = …; static int aspeed_clk_is_enabled(struct clk_hw *hw) { … } static int aspeed_clk_enable(struct clk_hw *hw) { … } static void aspeed_clk_disable(struct clk_hw *hw) { … } static const struct clk_ops aspeed_clk_gate_ops = …; static const u8 aspeed_resets[] = …; static int aspeed_reset_deassert(struct reset_controller_dev *rcdev, unsigned long id) { … } static int aspeed_reset_assert(struct reset_controller_dev *rcdev, unsigned long id) { … } static int aspeed_reset_status(struct reset_controller_dev *rcdev, unsigned long id) { … } static const struct reset_control_ops aspeed_reset_ops = …; static struct clk_hw *aspeed_clk_hw_register_gate(struct device *dev, const char *name, const char *parent_name, unsigned long flags, struct regmap *map, u8 clock_idx, u8 reset_idx, u8 clk_gate_flags, spinlock_t *lock) { … } static int aspeed_clk_probe(struct platform_device *pdev) { const struct aspeed_clk_soc_data *soc_data; struct device *dev = &pdev->dev; struct aspeed_reset *ar; struct regmap *map; struct clk_hw *hw; u32 val, rate; int i, ret; map = syscon_node_to_regmap(dev->of_node); if (IS_ERR(map)) { dev_err(dev, "no syscon regmap\n"); return PTR_ERR(map); } ar = devm_kzalloc(dev, sizeof(*ar), GFP_KERNEL); if (!ar) return -ENOMEM; ar->map = map; ar->rcdev.owner = THIS_MODULE; ar->rcdev.nr_resets = ARRAY_SIZE(aspeed_resets); ar->rcdev.ops = &aspeed_reset_ops; ar->rcdev.of_node = dev->of_node; ret = devm_reset_controller_register(dev, &ar->rcdev); if (ret) { dev_err(dev, "could not register reset controller\n"); return ret; } /* SoC generations share common layouts but have different divisors */ soc_data = of_device_get_match_data(dev); if (!soc_data) { dev_err(dev, "no match data for platform\n"); return -EINVAL; } /* UART clock div13 setting */ regmap_read(map, ASPEED_MISC_CTRL, &val); if (val & UART_DIV13_EN) rate = 24000000 / 13; else rate = 24000000; /* TODO: Find the parent data for the uart clock */ hw = clk_hw_register_fixed_rate(dev, "uart", NULL, 0, rate); if (IS_ERR(hw)) return PTR_ERR(hw); aspeed_clk_data->hws[ASPEED_CLK_UART] = hw; /* * Memory controller (M-PLL) PLL. This clock is configured by the * bootloader, and is exposed to Linux as a read-only clock rate. */ regmap_read(map, ASPEED_MPLL_PARAM, &val); hw = soc_data->calc_pll("mpll", val); if (IS_ERR(hw)) return PTR_ERR(hw); aspeed_clk_data->hws[ASPEED_CLK_MPLL] = hw; /* SD/SDIO clock divider and gate */ hw = clk_hw_register_gate(dev, "sd_extclk_gate", "hpll", 0, scu_base + ASPEED_CLK_SELECTION, 15, 0, &aspeed_clk_lock); if (IS_ERR(hw)) return PTR_ERR(hw); hw = clk_hw_register_divider_table(dev, "sd_extclk", "sd_extclk_gate", 0, scu_base + ASPEED_CLK_SELECTION, 12, 3, 0, soc_data->div_table, &aspeed_clk_lock); if (IS_ERR(hw)) return PTR_ERR(hw); aspeed_clk_data->hws[ASPEED_CLK_SDIO] = hw; /* MAC AHB bus clock divider */ hw = clk_hw_register_divider_table(dev, "mac", "hpll", 0, scu_base + ASPEED_CLK_SELECTION, 16, 3, 0, soc_data->mac_div_table, &aspeed_clk_lock); if (IS_ERR(hw)) return PTR_ERR(hw); aspeed_clk_data->hws[ASPEED_CLK_MAC] = hw; if (of_device_is_compatible(pdev->dev.of_node, "aspeed,ast2500-scu")) { /* RMII 50MHz RCLK */ hw = clk_hw_register_fixed_rate(dev, "mac12rclk", "hpll", 0, 50000000); if (IS_ERR(hw)) return PTR_ERR(hw); /* RMII1 50MHz (RCLK) output enable */ hw = clk_hw_register_gate(dev, "mac1rclk", "mac12rclk", 0, scu_base + ASPEED_MAC_CLK_DLY, 29, 0, &aspeed_clk_lock); if (IS_ERR(hw)) return PTR_ERR(hw); aspeed_clk_data->hws[ASPEED_CLK_MAC1RCLK] = hw; /* RMII2 50MHz (RCLK) output enable */ hw = clk_hw_register_gate(dev, "mac2rclk", "mac12rclk", 0, scu_base + ASPEED_MAC_CLK_DLY, 30, 0, &aspeed_clk_lock); if (IS_ERR(hw)) return PTR_ERR(hw); aspeed_clk_data->hws[ASPEED_CLK_MAC2RCLK] = hw; } /* LPC Host (LHCLK) clock divider */ hw = clk_hw_register_divider_table(dev, "lhclk", "hpll", 0, scu_base + ASPEED_CLK_SELECTION, 20, 3, 0, soc_data->div_table, &aspeed_clk_lock); if (IS_ERR(hw)) return PTR_ERR(hw); aspeed_clk_data->hws[ASPEED_CLK_LHCLK] = hw; /* P-Bus (BCLK) clock divider */ hw = clk_hw_register_divider_table(dev, "bclk", "hpll", 0, scu_base + ASPEED_CLK_SELECTION_2, 0, 2, 0, soc_data->div_table, &aspeed_clk_lock); if (IS_ERR(hw)) return PTR_ERR(hw); aspeed_clk_data->hws[ASPEED_CLK_BCLK] = hw; /* Fixed 24MHz clock */ hw = clk_hw_register_fixed_rate(NULL, "fixed-24m", "clkin", 0, 24000000); if (IS_ERR(hw)) return PTR_ERR(hw); aspeed_clk_data->hws[ASPEED_CLK_24M] = hw; hw = clk_hw_register_mux(dev, "eclk-mux", eclk_parent_names, ARRAY_SIZE(eclk_parent_names), 0, scu_base + ASPEED_CLK_SELECTION, 2, 0x3, 0, &aspeed_clk_lock); if (IS_ERR(hw)) return PTR_ERR(hw); aspeed_clk_data->hws[ASPEED_CLK_ECLK_MUX] = hw; hw = clk_hw_register_divider_table(dev, "eclk", "eclk-mux", 0, scu_base + ASPEED_CLK_SELECTION, 28, 3, 0, soc_data->eclk_div_table, &aspeed_clk_lock); if (IS_ERR(hw)) return PTR_ERR(hw); aspeed_clk_data->hws[ASPEED_CLK_ECLK] = hw; /* * TODO: There are a number of clocks that not included in this driver * as more information is required: * D2-PLL * D-PLL * YCLK * RGMII * RMII * UART[1..5] clock source mux */ for (i = 0; i < ARRAY_SIZE(aspeed_gates); i++) { const struct aspeed_gate_data *gd = &aspeed_gates[i]; u32 gate_flags; /* Special case: the USB port 1 clock (bit 14) is always * working the opposite way from the other ones. */ gate_flags = (gd->clock_idx == 14) ? 0 : CLK_GATE_SET_TO_DISABLE; hw = aspeed_clk_hw_register_gate(dev, gd->name, gd->parent_name, gd->flags, map, gd->clock_idx, gd->reset_idx, gate_flags, &aspeed_clk_lock); if (IS_ERR(hw)) return PTR_ERR(hw); aspeed_clk_data->hws[i] = hw; } return 0; }; static const struct of_device_id aspeed_clk_dt_ids[] = …; static struct platform_driver aspeed_clk_driver = …; builtin_platform_driver(…) …; static void __init aspeed_ast2400_cc(struct regmap *map) { … } static void __init aspeed_ast2500_cc(struct regmap *map) { struct clk_hw *hw; u32 val, freq, div; /* CLKIN is the crystal oscillator, 24 or 25MHz selected by strapping */ regmap_read(map, ASPEED_STRAP, &val); if (val & CLKIN_25MHZ_EN) freq = 25000000; else freq = 24000000; hw = clk_hw_register_fixed_rate(NULL, "clkin", NULL, 0, freq); pr_debug("clkin @%u MHz\n", freq / 1000000); /* * High-speed PLL clock derived from the crystal. This the CPU clock, * and we assume that it is enabled */ regmap_read(map, ASPEED_HPLL_PARAM, &val); aspeed_clk_data->hws[ASPEED_CLK_HPLL] = aspeed_ast2500_calc_pll("hpll", val); /* Strap bits 11:9 define the AXI/AHB clock frequency ratio (aka HCLK)*/ regmap_read(map, ASPEED_STRAP, &val); val = (val >> 9) & 0x7; WARN(val == 0, "strapping is zero: cannot determine ahb clock"); div = 2 * (val + 1); hw = clk_hw_register_fixed_factor(NULL, "ahb", "hpll", 0, 1, div); aspeed_clk_data->hws[ASPEED_CLK_AHB] = hw; /* APB clock clock selection register SCU08 (aka PCLK) */ regmap_read(map, ASPEED_CLK_SELECTION, &val); val = (val >> 23) & 0x7; div = 4 * (val + 1); hw = clk_hw_register_fixed_factor(NULL, "apb", "hpll", 0, 1, div); aspeed_clk_data->hws[ASPEED_CLK_APB] = hw; }; static void __init aspeed_cc_init(struct device_node *np) { struct regmap *map; u32 val; int ret; int i; scu_base = of_iomap(np, 0); if (!scu_base) return; aspeed_clk_data = kzalloc(struct_size(aspeed_clk_data, hws, ASPEED_NUM_CLKS), GFP_KERNEL); if (!aspeed_clk_data) return; aspeed_clk_data->num = ASPEED_NUM_CLKS; /* * This way all clocks fetched before the platform device probes, * except those we assign here for early use, will be deferred. */ for (i = 0; i < ASPEED_NUM_CLKS; i++) aspeed_clk_data->hws[i] = ERR_PTR(-EPROBE_DEFER); map = syscon_node_to_regmap(np); if (IS_ERR(map)) { pr_err("no syscon regmap\n"); return; } /* * We check that the regmap works on this very first access, * but as this is an MMIO-backed regmap, subsequent regmap * access is not going to fail and we skip error checks from * this point. */ ret = regmap_read(map, ASPEED_STRAP, &val); if (ret) { pr_err("failed to read strapping register\n"); return; } if (of_device_is_compatible(np, "aspeed,ast2400-scu")) aspeed_ast2400_cc(map); else if (of_device_is_compatible(np, "aspeed,ast2500-scu")) aspeed_ast2500_cc(map); else pr_err("unknown platform, failed to add clocks\n"); ret = of_clk_add_hw_provider(np, of_clk_hw_onecell_get, aspeed_clk_data); if (ret) pr_err("failed to add DT provider: %d\n", ret); }; CLK_OF_DECLARE_DRIVER(aspeed_cc_g5, "aspeed,ast2500-scu", aspeed_cc_init); CLK_OF_DECLARE_DRIVER(aspeed_cc_g4, "aspeed,ast2400-scu", aspeed_cc_init);
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