/* SPDX-License-Identifier: GPL-2.0-or-later */ /* * Freecale 85xx and 86xx Global Utilties register set * * Authors: Jeff Brown * Timur Tabi <[email protected]> * * Copyright 2004,2007,2012 Freescale Semiconductor, Inc */ #ifndef __FSL_GUTS_H__ #define __FSL_GUTS_H__ #include <linux/types.h> #include <linux/io.h> /* * Global Utility Registers. * * Not all registers defined in this structure are available on all chips, so * you are expected to know whether a given register actually exists on your * chip before you access it. * * Also, some registers are similar on different chips but have slightly * different names. In these cases, one name is chosen to avoid extraneous * #ifdefs. */ struct ccsr_guts { … } __attribute__ ((packed)); /* Alternate function signal multiplex control */ #define MPC85xx_PMUXCR_QE(x) … #ifdef CONFIG_PPC_86xx #define CCSR_GUTS_DMACR_DEV_SSI … #define CCSR_GUTS_DMACR_DEV_IR … /* * Set the DMACR register in the GUTS * * The DMACR register determines the source of initiated transfers for each * channel on each DMA controller. Rather than have a bunch of repetitive * macros for the bit patterns, we just have a function that calculates * them. * * guts: Pointer to GUTS structure * co: The DMA controller (0 or 1) * ch: The channel on the DMA controller (0, 1, 2, or 3) * device: The device to set as the source (CCSR_GUTS_DMACR_DEV_xx) */ static inline void guts_set_dmacr(struct ccsr_guts __iomem *guts, unsigned int co, unsigned int ch, unsigned int device) { unsigned int shift = 16 + (8 * (1 - co) + 2 * (3 - ch)); clrsetbits_be32(&guts->dmacr, 3 << shift, device << shift); } #define CCSR_GUTS_PMUXCR_LDPSEL … #define CCSR_GUTS_PMUXCR_SSI1_MASK … #define CCSR_GUTS_PMUXCR_SSI1_LA … #define CCSR_GUTS_PMUXCR_SSI1_HI … #define CCSR_GUTS_PMUXCR_SSI1_SSI … #define CCSR_GUTS_PMUXCR_SSI2_MASK … #define CCSR_GUTS_PMUXCR_SSI2_LA … #define CCSR_GUTS_PMUXCR_SSI2_HI … #define CCSR_GUTS_PMUXCR_SSI2_SSI … #define CCSR_GUTS_PMUXCR_LA_22_25_LA … #define CCSR_GUTS_PMUXCR_LA_22_25_HI … #define CCSR_GUTS_PMUXCR_DBGDRV … #define CCSR_GUTS_PMUXCR_DMA2_0 … #define CCSR_GUTS_PMUXCR_DMA2_3 … #define CCSR_GUTS_PMUXCR_DMA1_0 … #define CCSR_GUTS_PMUXCR_DMA1_3 … /* * Set the DMA external control bits in the GUTS * * The DMA external control bits in the PMUXCR are only meaningful for * channels 0 and 3. Any other channels are ignored. * * guts: Pointer to GUTS structure * co: The DMA controller (0 or 1) * ch: The channel on the DMA controller (0, 1, 2, or 3) * value: the new value for the bit (0 or 1) */ static inline void guts_set_pmuxcr_dma(struct ccsr_guts __iomem *guts, unsigned int co, unsigned int ch, unsigned int value) { if ((ch == 0) || (ch == 3)) { unsigned int shift = 2 * (co + 1) - (ch & 1) - 1; clrsetbits_be32(&guts->pmuxcr, 1 << shift, value << shift); } } #define CCSR_GUTS_CLKDVDR_PXCKEN … #define CCSR_GUTS_CLKDVDR_SSICKEN … #define CCSR_GUTS_CLKDVDR_PXCKINV … #define CCSR_GUTS_CLKDVDR_PXCKDLY_SHIFT … #define CCSR_GUTS_CLKDVDR_PXCKDLY_MASK … #define CCSR_GUTS_CLKDVDR_PXCKDLY … #define CCSR_GUTS_CLKDVDR_PXCLK_SHIFT … #define CCSR_GUTS_CLKDVDR_PXCLK_MASK … #define CCSR_GUTS_CLKDVDR_PXCLK … #define CCSR_GUTS_CLKDVDR_SSICLK_MASK … #define CCSR_GUTS_CLKDVDR_SSICLK … #endif struct ccsr_rcpm_v1 { … }; struct ccsr_rcpm_v2 { … }; #endif
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