// SPDX-License-Identifier: GPL-2.0-only /* * Copyright 2013 Freescale Semiconductor, Inc. * Copyright 2021 NXP * * clock driver for Freescale QorIQ SoCs. */ #define pr_fmt(fmt) … #include <dt-bindings/clock/fsl,qoriq-clockgen.h> #include <linux/clk.h> #include <linux/clk-provider.h> #include <linux/clkdev.h> #include <linux/fsl/guts.h> #include <linux/io.h> #include <linux/kernel.h> #include <linux/module.h> #include <linux/of_address.h> #include <linux/of.h> #include <linux/platform_device.h> #include <linux/slab.h> #define PLL_DIV1 … #define PLL_DIV2 … #define PLL_DIV3 … #define PLL_DIV4 … #define PLATFORM_PLL … #define CGA_PLL1 … #define CGA_PLL2 … #define CGA_PLL3 … #define CGA_PLL4 … #define CGB_PLL1 … #define CGB_PLL2 … #define MAX_PLL_DIV … struct clockgen_pll_div { … }; struct clockgen_pll { … }; #define CLKSEL_VALID … #define CLKSEL_80PCT … struct clockgen_sourceinfo { … }; #define NUM_MUX_PARENTS … struct clockgen_muxinfo { … }; #define NUM_HWACCEL … #define NUM_CMUX … struct clockgen; /* * cmux freq must be >= platform pll. * If not set, cmux freq must be >= platform pll/2 */ #define CG_CMUX_GE_PLAT … #define CG_PLL_8BIT … #define CG_VER3 … #define CG_LITTLE_ENDIAN … struct clockgen_chipinfo { … }; struct clockgen { … }; static struct clockgen clockgen; static bool add_cpufreq_dev __initdata; static void cg_out(struct clockgen *cg, u32 val, u32 __iomem *reg) { … } static u32 cg_in(struct clockgen *cg, u32 __iomem *reg) { … } static const struct clockgen_muxinfo p2041_cmux_grp1 = …; static const struct clockgen_muxinfo p2041_cmux_grp2 = …; static const struct clockgen_muxinfo p5020_cmux_grp1 = …; static const struct clockgen_muxinfo p5020_cmux_grp2 = …; static const struct clockgen_muxinfo p5040_cmux_grp1 = …; static const struct clockgen_muxinfo p5040_cmux_grp2 = …; static const struct clockgen_muxinfo p4080_cmux_grp1 = …; static const struct clockgen_muxinfo p4080_cmux_grp2 = …; static const struct clockgen_muxinfo t1023_cmux = …; static const struct clockgen_muxinfo t1040_cmux = …; static const struct clockgen_muxinfo clockgen2_cmux_cga = …; static const struct clockgen_muxinfo clockgen2_cmux_cga12 = …; static const struct clockgen_muxinfo clockgen2_cmux_cgb = …; static const struct clockgen_muxinfo ls1021a_cmux = …; static const struct clockgen_muxinfo ls1028a_hwa1 = …; static const struct clockgen_muxinfo ls1028a_hwa2 = …; static const struct clockgen_muxinfo ls1028a_hwa3 = …; static const struct clockgen_muxinfo ls1028a_hwa4 = …; static const struct clockgen_muxinfo ls1043a_hwa1 = …; static const struct clockgen_muxinfo ls1043a_hwa2 = …; static const struct clockgen_muxinfo ls1046a_hwa1 = …; static const struct clockgen_muxinfo ls1046a_hwa2 = …; static const struct clockgen_muxinfo ls1088a_hwa1 = …; static const struct clockgen_muxinfo ls1088a_hwa2 = …; static const struct clockgen_muxinfo ls1012a_cmux = …; static const struct clockgen_muxinfo t1023_hwa1 = …; static const struct clockgen_muxinfo t1023_hwa2 = …; static const struct clockgen_muxinfo t2080_hwa1 = …; static const struct clockgen_muxinfo t2080_hwa2 = …; static const struct clockgen_muxinfo t4240_hwa1 = …; static const struct clockgen_muxinfo t4240_hwa4 = …; static const struct clockgen_muxinfo t4240_hwa5 = …; #define RCWSR7_FM1_CLK_SEL … #define RCWSR7_FM2_CLK_SEL … #define RCWSR7_HWA_ASYNC_DIV … static void __init p2041_init_periph(struct clockgen *cg) { … } static void __init p4080_init_periph(struct clockgen *cg) { … } static void __init p5020_init_periph(struct clockgen *cg) { … } static void __init p5040_init_periph(struct clockgen *cg) { … } static void __init t1023_init_periph(struct clockgen *cg) { … } static void __init t1040_init_periph(struct clockgen *cg) { … } static void __init t2080_init_periph(struct clockgen *cg) { … } static void __init t4240_init_periph(struct clockgen *cg) { … } static const struct clockgen_chipinfo chipinfo[] = …; struct mux_hwclock { … }; #define to_mux_hwclock(p) … #define CLKSEL_MASK … #define CLKSEL_SHIFT … static int mux_set_parent(struct clk_hw *hw, u8 idx) { … } static u8 mux_get_parent(struct clk_hw *hw) { … } static const struct clk_ops cmux_ops = …; /* * Don't allow setting for now, as the clock options haven't been * sanitized for additional restrictions. */ static const struct clk_ops hwaccel_ops = …; static const struct clockgen_pll_div *get_pll_div(struct clockgen *cg, struct mux_hwclock *hwc, int idx) { … } static struct clk * __init create_mux_common(struct clockgen *cg, struct mux_hwclock *hwc, const struct clk_ops *ops, unsigned long min_rate, unsigned long max_rate, unsigned long pct80_rate, const char *fmt, int idx) { … } static struct clk * __init create_one_cmux(struct clockgen *cg, int idx) { … } static struct clk * __init create_one_hwaccel(struct clockgen *cg, int idx) { … } static void __init create_muxes(struct clockgen *cg) { … } static void __init _clockgen_init(struct device_node *np, bool legacy); /* * Legacy nodes may get probed before the parent clockgen node. * It is assumed that device trees with legacy nodes will not * contain a "clocks" property -- otherwise the input clocks may * not be initialized at this point. */ static void __init legacy_init_clockgen(struct device_node *np) { … } /* Legacy node */ static void __init core_mux_init(struct device_node *np) { … } static struct clk __init *sysclk_from_fixed(struct device_node *node, const char *name) { … } static struct clk __init *input_clock(const char *name, struct clk *clk) { … } static struct clk __init *input_clock_by_name(const char *name, const char *dtname) { … } static struct clk __init *input_clock_by_index(const char *name, int idx) { … } static struct clk * __init create_sysclk(const char *name) { … } static struct clk * __init create_coreclk(const char *name) { … } /* Legacy node */ static void __init sysclk_init(struct device_node *node) { … } #define PLL_KILL … static void __init create_one_pll(struct clockgen *cg, int idx) { … } static void __init create_plls(struct clockgen *cg) { … } static void __init legacy_pll_init(struct device_node *np, int idx) { … } /* Legacy node */ static void __init pltfrm_pll_init(struct device_node *np) { … } /* Legacy node */ static void __init core_pll_init(struct device_node *np) { … } static struct clk *clockgen_clk_get(struct of_phandle_args *clkspec, void *data) { … } #ifdef CONFIG_PPC #include <asm/mpc85xx.h> static const u32 a4510_svrs[] __initconst = { (SVR_P2040 << 8) | 0x10, /* P2040 1.0 */ (SVR_P2040 << 8) | 0x11, /* P2040 1.1 */ (SVR_P2041 << 8) | 0x10, /* P2041 1.0 */ (SVR_P2041 << 8) | 0x11, /* P2041 1.1 */ (SVR_P3041 << 8) | 0x10, /* P3041 1.0 */ (SVR_P3041 << 8) | 0x11, /* P3041 1.1 */ (SVR_P4040 << 8) | 0x20, /* P4040 2.0 */ (SVR_P4080 << 8) | 0x20, /* P4080 2.0 */ (SVR_P5010 << 8) | 0x10, /* P5010 1.0 */ (SVR_P5010 << 8) | 0x20, /* P5010 2.0 */ (SVR_P5020 << 8) | 0x10, /* P5020 1.0 */ (SVR_P5021 << 8) | 0x10, /* P5021 1.0 */ (SVR_P5040 << 8) | 0x10, /* P5040 1.0 */ }; #define SVR_SECURITY … static bool __init has_erratum_a4510(void) { u32 svr = mfspr(SPRN_SVR); int i; svr &= ~SVR_SECURITY; for (i = 0; i < ARRAY_SIZE(a4510_svrs); i++) { if (svr == a4510_svrs[i]) return true; } return false; } #else static bool __init has_erratum_a4510(void) { … } #endif static void __init _clockgen_init(struct device_node *np, bool legacy) { … } static void __init clockgen_init(struct device_node *np) { … } static int __init clockgen_cpufreq_init(void) { … } device_initcall(clockgen_cpufreq_init); CLK_OF_DECLARE(qoriq_clockgen_1, "fsl,qoriq-clockgen-1.0", clockgen_init); CLK_OF_DECLARE(qoriq_clockgen_2, "fsl,qoriq-clockgen-2.0", clockgen_init); CLK_OF_DECLARE(qoriq_clockgen_b4420, "fsl,b4420-clockgen", clockgen_init); CLK_OF_DECLARE(qoriq_clockgen_b4860, "fsl,b4860-clockgen", clockgen_init); CLK_OF_DECLARE(qoriq_clockgen_ls1012a, "fsl,ls1012a-clockgen", clockgen_init); CLK_OF_DECLARE(qoriq_clockgen_ls1021a, "fsl,ls1021a-clockgen", clockgen_init); CLK_OF_DECLARE(qoriq_clockgen_ls1028a, "fsl,ls1028a-clockgen", clockgen_init); CLK_OF_DECLARE(qoriq_clockgen_ls1043a, "fsl,ls1043a-clockgen", clockgen_init); CLK_OF_DECLARE(qoriq_clockgen_ls1046a, "fsl,ls1046a-clockgen", clockgen_init); CLK_OF_DECLARE(qoriq_clockgen_ls1088a, "fsl,ls1088a-clockgen", clockgen_init); CLK_OF_DECLARE(qoriq_clockgen_ls2080a, "fsl,ls2080a-clockgen", clockgen_init); CLK_OF_DECLARE(qoriq_clockgen_lx2160a, "fsl,lx2160a-clockgen", clockgen_init); CLK_OF_DECLARE(qoriq_clockgen_p2041, "fsl,p2041-clockgen", clockgen_init); CLK_OF_DECLARE(qoriq_clockgen_p3041, "fsl,p3041-clockgen", clockgen_init); CLK_OF_DECLARE(qoriq_clockgen_p4080, "fsl,p4080-clockgen", clockgen_init); CLK_OF_DECLARE(qoriq_clockgen_p5020, "fsl,p5020-clockgen", clockgen_init); CLK_OF_DECLARE(qoriq_clockgen_p5040, "fsl,p5040-clockgen", clockgen_init); CLK_OF_DECLARE(qoriq_clockgen_t1023, "fsl,t1023-clockgen", clockgen_init); CLK_OF_DECLARE(qoriq_clockgen_t1040, "fsl,t1040-clockgen", clockgen_init); CLK_OF_DECLARE(qoriq_clockgen_t2080, "fsl,t2080-clockgen", clockgen_init); CLK_OF_DECLARE(qoriq_clockgen_t4240, "fsl,t4240-clockgen", clockgen_init); /* Legacy nodes */ CLK_OF_DECLARE(qoriq_sysclk_1, "fsl,qoriq-sysclk-1.0", sysclk_init); CLK_OF_DECLARE(qoriq_sysclk_2, "fsl,qoriq-sysclk-2.0", sysclk_init); CLK_OF_DECLARE(qoriq_core_pll_1, "fsl,qoriq-core-pll-1.0", core_pll_init); CLK_OF_DECLARE(qoriq_core_pll_2, "fsl,qoriq-core-pll-2.0", core_pll_init); CLK_OF_DECLARE(qoriq_core_mux_1, "fsl,qoriq-core-mux-1.0", core_mux_init); CLK_OF_DECLARE(qoriq_core_mux_2, "fsl,qoriq-core-mux-2.0", core_mux_init); CLK_OF_DECLARE(qoriq_pltfrm_pll_1, "fsl,qoriq-platform-pll-1.0", pltfrm_pll_init); CLK_OF_DECLARE(qoriq_pltfrm_pll_2, "fsl,qoriq-platform-pll-2.0", pltfrm_pll_init);
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