/* SPDX-License-Identifier: GPL-2.0-or-later */ /* * clk-si5351.h: Skyworks / Silicon Labs Si5351A/B/C I2C Clock Generator * * Sebastian Hesselbarth <[email protected]> * Rabeeh Khoury <[email protected]> */ #ifndef _CLK_SI5351_H_ #define _CLK_SI5351_H_ #define SI5351_BUS_BASE_ADDR … #define SI5351_PLL_VCO_MIN … #define SI5351_PLL_VCO_MAX … #define SI5351_MULTISYNTH_MIN_FREQ … #define SI5351_MULTISYNTH_DIVBY4_FREQ … #define SI5351_MULTISYNTH_MAX_FREQ … #define SI5351_MULTISYNTH67_MAX_FREQ … #define SI5351_CLKOUT_MIN_FREQ … #define SI5351_CLKOUT_MAX_FREQ … #define SI5351_CLKOUT67_MAX_FREQ … #define SI5351_PLL_A_MIN … #define SI5351_PLL_A_MAX … #define SI5351_PLL_B_MAX … #define SI5351_PLL_C_MAX … #define SI5351_MULTISYNTH_A_MIN … #define SI5351_MULTISYNTH_A_MAX … #define SI5351_MULTISYNTH67_A_MAX … #define SI5351_MULTISYNTH_B_MAX … #define SI5351_MULTISYNTH_C_MAX … #define SI5351_MULTISYNTH_P1_MAX … #define SI5351_MULTISYNTH_P2_MAX … #define SI5351_MULTISYNTH_P3_MAX … #define SI5351_DEVICE_STATUS … #define SI5351_INTERRUPT_STATUS … #define SI5351_INTERRUPT_MASK … #define SI5351_STATUS_SYS_INIT … #define SI5351_STATUS_LOL_B … #define SI5351_STATUS_LOL_A … #define SI5351_STATUS_LOS … #define SI5351_OUTPUT_ENABLE_CTRL … #define SI5351_OEB_PIN_ENABLE_CTRL … #define SI5351_PLL_INPUT_SOURCE … #define SI5351_CLKIN_DIV_MASK … #define SI5351_CLKIN_DIV_1 … #define SI5351_CLKIN_DIV_2 … #define SI5351_CLKIN_DIV_4 … #define SI5351_CLKIN_DIV_8 … #define SI5351_PLLB_SOURCE … #define SI5351_PLLA_SOURCE … #define SI5351_CLK0_CTRL … #define SI5351_CLK1_CTRL … #define SI5351_CLK2_CTRL … #define SI5351_CLK3_CTRL … #define SI5351_CLK4_CTRL … #define SI5351_CLK5_CTRL … #define SI5351_CLK6_CTRL … #define SI5351_CLK7_CTRL … #define SI5351_CLK_POWERDOWN … #define SI5351_CLK_INTEGER_MODE … #define SI5351_CLK_PLL_SELECT … #define SI5351_CLK_INVERT … #define SI5351_CLK_INPUT_MASK … #define SI5351_CLK_INPUT_XTAL … #define SI5351_CLK_INPUT_CLKIN … #define SI5351_CLK_INPUT_MULTISYNTH_0_4 … #define SI5351_CLK_INPUT_MULTISYNTH_N … #define SI5351_CLK_DRIVE_STRENGTH_MASK … #define SI5351_CLK_DRIVE_STRENGTH_2MA … #define SI5351_CLK_DRIVE_STRENGTH_4MA … #define SI5351_CLK_DRIVE_STRENGTH_6MA … #define SI5351_CLK_DRIVE_STRENGTH_8MA … #define SI5351_CLK3_0_DISABLE_STATE … #define SI5351_CLK7_4_DISABLE_STATE … #define SI5351_CLK_DISABLE_STATE_MASK … #define SI5351_CLK_DISABLE_STATE_LOW … #define SI5351_CLK_DISABLE_STATE_HIGH … #define SI5351_CLK_DISABLE_STATE_FLOAT … #define SI5351_CLK_DISABLE_STATE_NEVER … #define SI5351_PARAMETERS_LENGTH … #define SI5351_PLLA_PARAMETERS … #define SI5351_PLLB_PARAMETERS … #define SI5351_CLK0_PARAMETERS … #define SI5351_CLK1_PARAMETERS … #define SI5351_CLK2_PARAMETERS … #define SI5351_CLK3_PARAMETERS … #define SI5351_CLK4_PARAMETERS … #define SI5351_CLK5_PARAMETERS … #define SI5351_CLK6_PARAMETERS … #define SI5351_CLK7_PARAMETERS … #define SI5351_CLK6_7_OUTPUT_DIVIDER … #define SI5351_OUTPUT_CLK_DIV_MASK … #define SI5351_OUTPUT_CLK6_DIV_MASK … #define SI5351_OUTPUT_CLK_DIV_SHIFT … #define SI5351_OUTPUT_CLK_DIV6_SHIFT … #define SI5351_OUTPUT_CLK_DIV_1 … #define SI5351_OUTPUT_CLK_DIV_2 … #define SI5351_OUTPUT_CLK_DIV_4 … #define SI5351_OUTPUT_CLK_DIV_8 … #define SI5351_OUTPUT_CLK_DIV_16 … #define SI5351_OUTPUT_CLK_DIV_32 … #define SI5351_OUTPUT_CLK_DIV_64 … #define SI5351_OUTPUT_CLK_DIV_128 … #define SI5351_OUTPUT_CLK_DIVBY4 … #define SI5351_SSC_PARAM0 … #define SI5351_SSC_PARAM1 … #define SI5351_SSC_PARAM2 … #define SI5351_SSC_PARAM3 … #define SI5351_SSC_PARAM4 … #define SI5351_SSC_PARAM5 … #define SI5351_SSC_PARAM6 … #define SI5351_SSC_PARAM7 … #define SI5351_SSC_PARAM8 … #define SI5351_SSC_PARAM9 … #define SI5351_SSC_PARAM10 … #define SI5351_SSC_PARAM11 … #define SI5351_SSC_PARAM12 … #define SI5351_VXCO_PARAMETERS_LOW … #define SI5351_VXCO_PARAMETERS_MID … #define SI5351_VXCO_PARAMETERS_HIGH … #define SI5351_CLK0_PHASE_OFFSET … #define SI5351_CLK1_PHASE_OFFSET … #define SI5351_CLK2_PHASE_OFFSET … #define SI5351_CLK3_PHASE_OFFSET … #define SI5351_CLK4_PHASE_OFFSET … #define SI5351_CLK5_PHASE_OFFSET … #define SI5351_PLL_RESET … #define SI5351_PLL_RESET_B … #define SI5351_PLL_RESET_A … #define SI5351_CRYSTAL_LOAD … #define SI5351_CRYSTAL_LOAD_MASK … #define SI5351_CRYSTAL_LOAD_6PF … #define SI5351_CRYSTAL_LOAD_8PF … #define SI5351_CRYSTAL_LOAD_10PF … #define SI5351_FANOUT_ENABLE … #define SI5351_CLKIN_ENABLE … #define SI5351_XTAL_ENABLE … #define SI5351_MULTISYNTH_ENABLE … /** * enum si5351_variant - SiLabs Si5351 chip variant * @SI5351_VARIANT_A: Si5351A (8 output clocks, XTAL input) * @SI5351_VARIANT_A3: Si5351A MSOP10 (3 output clocks, XTAL input) * @SI5351_VARIANT_B: Si5351B (8 output clocks, XTAL/VXCO input) * @SI5351_VARIANT_C: Si5351C (8 output clocks, XTAL/CLKIN input) */ enum si5351_variant { … }; #endif
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