linux/drivers/clk/clk-sp7021.c

// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
/*
 * Copyright (C) Sunplus Technology Co., Ltd.
 *       All rights reserved.
 */
#include <linux/module.h>
#include <linux/clk-provider.h>
#include <linux/of.h>
#include <linux/bitfield.h>
#include <linux/slab.h>
#include <linux/io.h>
#include <linux/err.h>
#include <linux/platform_device.h>

#include <dt-bindings/clock/sunplus,sp7021-clkc.h>

/* speical div_width values for PLLTV/PLLA */
#define DIV_TV …
#define DIV_A …

/* PLLTV parameters */
enum { … };

#define MASK_SEL_FRA …
#define MASK_SDM_MOD …
#define MASK_PH_SEL …
#define MASK_NFRA …
#define MASK_DIVR …
#define MASK_DIVN …
#define MASK_DIVM …

/* HIWORD_MASK FIELD_PREP */
#define HWM_FIELD_PREP(mask, value) …

struct sp_pll { … };

#define to_sp_pll(_hw) …

struct sp_clk_gate_info { … };

static const struct sp_clk_gate_info sp_clk_gates[] = …;

#define _M …
#define F_27M …

/*********************************** PLL_TV **********************************/

/* TODO: set proper FVCO range */
#define FVCO_MIN …
#define FVCO_MAX …

#define F_MIN …
#define F_MAX …

static long plltv_integer_div(struct sp_pll *clk, unsigned long freq)
{ … }

/* parameters for PLLTV fractional divider */
static const u32 pt[][5] = …;

static const u32 sdm_mod_vals[] = …;

static long plltv_fractional_div(struct sp_pll *clk, unsigned long freq)
{ … }

static long plltv_div(struct sp_pll *clk, unsigned long freq)
{ … }

static int plltv_set_rate(struct sp_pll *clk)
{ … }

/*********************************** PLL_A ***********************************/

/* from Q628_PLLs_REG_setting.xlsx */
static const struct { … } pa[] = …;

static int plla_set_rate(struct sp_pll *clk)
{ … }

static long plla_round_rate(struct sp_pll *clk, unsigned long rate)
{ … }

/********************************** SP_PLL ***********************************/

static long sp_pll_calc_div(struct sp_pll *clk, unsigned long rate)
{ … }

static long sp_pll_round_rate(struct clk_hw *hw, unsigned long rate,
			      unsigned long *prate)
{ … }

static unsigned long sp_pll_recalc_rate(struct clk_hw *hw,
					unsigned long prate)
{ … }

static int sp_pll_set_rate(struct clk_hw *hw, unsigned long rate,
			   unsigned long prate)
{ … }

static int sp_pll_enable(struct clk_hw *hw)
{ … }

static void sp_pll_disable(struct clk_hw *hw)
{ … }

static int sp_pll_is_enabled(struct clk_hw *hw)
{ … }

static const struct clk_ops sp_pll_ops = …;

static const struct clk_ops sp_pll_sub_ops = …;

static struct clk_hw *sp_pll_register(struct device *dev, const char *name,
				      const struct clk_parent_data *parent_data,
				      void __iomem *reg, int pd_bit, int bp_bit,
				      unsigned long brate, int shift, int width,
				      unsigned long flags)
{ … }

#define PLLA_CTL …
#define PLLE_CTL …
#define PLLF_CTL …
#define PLLTV_CTL …

static int sp7021_clk_probe(struct platform_device *pdev)
{ … }

static const struct of_device_id sp7021_clk_dt_ids[] = …;
MODULE_DEVICE_TABLE(of, sp7021_clk_dt_ids);

static struct platform_driver sp7021_clk_driver = …;
module_platform_driver(…) …;

MODULE_AUTHOR(…) …;
MODULE_LICENSE(…) …;
MODULE_DESCRIPTION(…) …;