// SPDX-License-Identifier: GPL-2.0-or-later /* * clk-xgene.c - AppliedMicro X-Gene Clock Interface * * Copyright (c) 2013, Applied Micro Circuits Corporation * Author: Loc Ho <[email protected]> */ #include <linux/module.h> #include <linux/spinlock.h> #include <linux/io.h> #include <linux/of.h> #include <linux/clkdev.h> #include <linux/clk-provider.h> #include <linux/of_address.h> /* Register SCU_PCPPLL bit fields */ #define N_DIV_RD(src) … #define SC_N_DIV_RD(src) … #define SC_OUTDIV2(src) … /* Register SCU_SOCPLL bit fields */ #define CLKR_RD(src) … #define CLKOD_RD(src) … #define REGSPEC_RESET_F1_MASK … #define CLKF_RD(src) … #define XGENE_CLK_DRIVER_VER … static DEFINE_SPINLOCK(clk_lock); static inline u32 xgene_clk_read(void __iomem *csr) { … } static inline void xgene_clk_write(u32 data, void __iomem *csr) { … } /* PLL Clock */ enum xgene_pll_type { … }; struct xgene_clk_pll { … }; #define to_xgene_clk_pll(_hw) … static int xgene_clk_pll_is_enabled(struct clk_hw *hw) { … } static unsigned long xgene_clk_pll_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) { … } static const struct clk_ops xgene_clk_pll_ops = …; static struct clk *xgene_register_clk_pll(struct device *dev, const char *name, const char *parent_name, unsigned long flags, void __iomem *reg, u32 pll_offset, u32 type, spinlock_t *lock, int version) { … } static int xgene_pllclk_version(struct device_node *np) { … } static void xgene_pllclk_init(struct device_node *np, enum xgene_pll_type pll_type) { … } static void xgene_socpllclk_init(struct device_node *np) { … } static void xgene_pcppllclk_init(struct device_node *np) { … } /** * struct xgene_clk_pmd - PMD clock * * @hw: handle between common and hardware-specific interfaces * @reg: register containing the fractional scale multiplier (scaler) * @shift: shift to the unit bit field * @mask: mask to the unit bit field * @denom: 1/denominator unit * @lock: register lock * @flags: XGENE_CLK_PMD_SCALE_INVERTED - By default the scaler is the value read * from the register plus one. For example, * 0 for (0 + 1) / denom, * 1 for (1 + 1) / denom and etc. * If this flag is set, it is * 0 for (denom - 0) / denom, * 1 for (denom - 1) / denom and etc. */ struct xgene_clk_pmd { … }; #define to_xgene_clk_pmd(_hw) … #define XGENE_CLK_PMD_SCALE_INVERTED … #define XGENE_CLK_PMD_SHIFT … #define XGENE_CLK_PMD_WIDTH … static unsigned long xgene_clk_pmd_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) { … } static long xgene_clk_pmd_round_rate(struct clk_hw *hw, unsigned long rate, unsigned long *parent_rate) { … } static int xgene_clk_pmd_set_rate(struct clk_hw *hw, unsigned long rate, unsigned long parent_rate) { … } static const struct clk_ops xgene_clk_pmd_ops = …; static struct clk * xgene_register_clk_pmd(struct device *dev, const char *name, const char *parent_name, unsigned long flags, void __iomem *reg, u8 shift, u8 width, u64 denom, u32 clk_flags, spinlock_t *lock) { … } static void xgene_pmdclk_init(struct device_node *np) { … } /* IP Clock */ struct xgene_dev_parameters { … }; struct xgene_clk { … }; #define to_xgene_clk(_hw) … static int xgene_clk_enable(struct clk_hw *hw) { … } static void xgene_clk_disable(struct clk_hw *hw) { … } static int xgene_clk_is_enabled(struct clk_hw *hw) { … } static unsigned long xgene_clk_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) { … } static int xgene_clk_set_rate(struct clk_hw *hw, unsigned long rate, unsigned long parent_rate) { … } static long xgene_clk_round_rate(struct clk_hw *hw, unsigned long rate, unsigned long *prate) { … } static const struct clk_ops xgene_clk_ops = …; static struct clk *xgene_register_clk(struct device *dev, const char *name, const char *parent_name, struct xgene_dev_parameters *parameters, spinlock_t *lock) { … } static void __init xgene_devclk_init(struct device_node *np) { … } CLK_OF_DECLARE(xgene_socpll_clock, "apm,xgene-socpll-clock", xgene_socpllclk_init); CLK_OF_DECLARE(xgene_pcppll_clock, "apm,xgene-pcppll-clock", xgene_pcppllclk_init); CLK_OF_DECLARE(xgene_pmd_clock, "apm,xgene-pmd-clock", xgene_pmdclk_init); CLK_OF_DECLARE(xgene_socpll_v2_clock, "apm,xgene-socpll-v2-clock", xgene_socpllclk_init); CLK_OF_DECLARE(xgene_pcppll_v2_clock, "apm,xgene-pcppll-v2-clock", xgene_pcppllclk_init); CLK_OF_DECLARE(xgene_dev_clock, "apm,xgene-device-clock", xgene_devclk_init);
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