/* SPDX-License-Identifier: GPL-2.0 */ // (C) 2017-2018 Synopsys, Inc. (www.synopsys.com) /* * Synopsys DesignWare AXI DMA Controller driver. * * Author: Eugeniy Paltsev <[email protected]> */ #ifndef _AXI_DMA_PLATFORM_H #define _AXI_DMA_PLATFORM_H #include <linux/bitops.h> #include <linux/clk.h> #include <linux/device.h> #include <linux/dmaengine.h> #include <linux/types.h> #include "../virt-dma.h" #define DMAC_MAX_CHANNELS … #define DMAC_MAX_MASTERS … #define DMAC_MAX_BLK_SIZE … struct dw_axi_dma_hcfg { … }; struct axi_dma_chan { … }; struct dw_axi_dma { … }; struct axi_dma_chip { … }; /* LLI == Linked List Item */ struct __packed axi_dma_lli { … }; struct axi_dma_hw_desc { … }; struct axi_dma_desc { … }; struct axi_dma_chan_config { … }; static inline struct device *dchan2dev(struct dma_chan *dchan) { … } static inline struct device *chan2dev(struct axi_dma_chan *chan) { … } static inline struct axi_dma_desc *vd_to_axi_desc(struct virt_dma_desc *vd) { … } static inline struct axi_dma_chan *vc_to_axi_dma_chan(struct virt_dma_chan *vc) { … } static inline struct axi_dma_chan *dchan_to_axi_dma_chan(struct dma_chan *dchan) { … } #define COMMON_REG_LEN … #define CHAN_REG_LEN … /* Common registers offset */ #define DMAC_ID … #define DMAC_COMPVER … #define DMAC_CFG … #define DMAC_CHEN … #define DMAC_CHEN_L … #define DMAC_CHEN_H … #define DMAC_CHSUSPREG … #define DMAC_CHABORTREG … #define DMAC_INTSTATUS … #define DMAC_COMMON_INTCLEAR … #define DMAC_COMMON_INTSTATUS_ENA … #define DMAC_COMMON_INTSIGNAL_ENA … #define DMAC_COMMON_INTSTATUS … #define DMAC_RESET … /* DMA channel registers offset */ #define CH_SAR … #define CH_DAR … #define CH_BLOCK_TS … #define CH_CTL … #define CH_CTL_L … #define CH_CTL_H … #define CH_CFG … #define CH_CFG_L … #define CH_CFG_H … #define CH_LLP … #define CH_STATUS … #define CH_SWHSSRC … #define CH_SWHSDST … #define CH_BLK_TFR_RESUMEREQ … #define CH_AXI_ID … #define CH_AXI_QOS … #define CH_SSTAT … #define CH_DSTAT … #define CH_SSTATAR … #define CH_DSTATAR … #define CH_INTSTATUS_ENA … #define CH_INTSTATUS … #define CH_INTSIGNAL_ENA … #define CH_INTCLEAR … /* These Apb registers are used by Intel KeemBay SoC */ #define DMAC_APB_CFG … #define DMAC_APB_STAT … #define DMAC_APB_DEBUG_STAT_0 … #define DMAC_APB_DEBUG_STAT_1 … #define DMAC_APB_HW_HS_SEL_0 … #define DMAC_APB_HW_HS_SEL_1 … #define DMAC_APB_LPI … #define DMAC_APB_BYTE_WR_CH_EN … #define DMAC_APB_HALFWORD_WR_CH_EN … #define UNUSED_CHANNEL … #define DMA_APB_HS_SEL_BIT_SIZE … #define DMA_APB_HS_SEL_MASK … #define MAX_BLOCK_SIZE … #define DMA_REG_MAP_CH_REF … /* DMAC_CFG */ #define DMAC_EN_POS … #define DMAC_EN_MASK … #define INT_EN_POS … #define INT_EN_MASK … /* DMAC_CHEN */ #define DMAC_CHAN_EN_SHIFT … #define DMAC_CHAN_EN_WE_SHIFT … #define DMAC_CHAN_SUSP_SHIFT … #define DMAC_CHAN_SUSP_WE_SHIFT … /* DMAC_CHEN2 */ #define DMAC_CHAN_EN2_WE_SHIFT … /* DMAC CHAN BLOCKS */ #define DMAC_CHAN_BLOCK_SHIFT … #define DMAC_CHAN_16 … /* DMAC_CHSUSP */ #define DMAC_CHAN_SUSP2_SHIFT … #define DMAC_CHAN_SUSP2_WE_SHIFT … /* CH_CTL_H */ #define CH_CTL_H_ARLEN_EN … #define CH_CTL_H_ARLEN_POS … #define CH_CTL_H_AWLEN_EN … #define CH_CTL_H_AWLEN_POS … enum { … }; #define CH_CTL_H_LLI_LAST … #define CH_CTL_H_LLI_VALID … /* CH_CTL_L */ #define CH_CTL_L_LAST_WRITE_EN … #define CH_CTL_L_DST_MSIZE_POS … #define CH_CTL_L_SRC_MSIZE_POS … enum { … }; #define CH_CTL_L_DST_WIDTH_POS … #define CH_CTL_L_SRC_WIDTH_POS … #define CH_CTL_L_DST_INC_POS … #define CH_CTL_L_SRC_INC_POS … enum { … }; #define CH_CTL_L_DST_MAST … #define CH_CTL_L_SRC_MAST … /* CH_CFG_H */ #define CH_CFG_H_PRIORITY_POS … #define CH_CFG_H_DST_PER_POS … #define CH_CFG_H_SRC_PER_POS … #define CH_CFG_H_HS_SEL_DST_POS … #define CH_CFG_H_HS_SEL_SRC_POS … enum { … }; #define CH_CFG_H_TT_FC_POS … enum { … }; /* CH_CFG_L */ #define CH_CFG_L_DST_MULTBLK_TYPE_POS … #define CH_CFG_L_SRC_MULTBLK_TYPE_POS … enum { … }; /* CH_CFG2 */ #define CH_CFG2_L_SRC_PER_POS … #define CH_CFG2_L_DST_PER_POS … #define CH_CFG2_H_TT_FC_POS … #define CH_CFG2_H_HS_SEL_SRC_POS … #define CH_CFG2_H_HS_SEL_DST_POS … #define CH_CFG2_H_PRIORITY_POS … /** * DW AXI DMA channel interrupts * * @DWAXIDMAC_IRQ_NONE: Bitmask of no one interrupt * @DWAXIDMAC_IRQ_BLOCK_TRF: Block transfer complete * @DWAXIDMAC_IRQ_DMA_TRF: Dma transfer complete * @DWAXIDMAC_IRQ_SRC_TRAN: Source transaction complete * @DWAXIDMAC_IRQ_DST_TRAN: Destination transaction complete * @DWAXIDMAC_IRQ_SRC_DEC_ERR: Source decode error * @DWAXIDMAC_IRQ_DST_DEC_ERR: Destination decode error * @DWAXIDMAC_IRQ_SRC_SLV_ERR: Source slave error * @DWAXIDMAC_IRQ_DST_SLV_ERR: Destination slave error * @DWAXIDMAC_IRQ_LLI_RD_DEC_ERR: LLI read decode error * @DWAXIDMAC_IRQ_LLI_WR_DEC_ERR: LLI write decode error * @DWAXIDMAC_IRQ_LLI_RD_SLV_ERR: LLI read slave error * @DWAXIDMAC_IRQ_LLI_WR_SLV_ERR: LLI write slave error * @DWAXIDMAC_IRQ_INVALID_ERR: LLI invalid error or Shadow register error * @DWAXIDMAC_IRQ_MULTIBLKTYPE_ERR: Slave Interface Multiblock type error * @DWAXIDMAC_IRQ_DEC_ERR: Slave Interface decode error * @DWAXIDMAC_IRQ_WR2RO_ERR: Slave Interface write to read only error * @DWAXIDMAC_IRQ_RD2RWO_ERR: Slave Interface read to write only error * @DWAXIDMAC_IRQ_WRONCHEN_ERR: Slave Interface write to channel error * @DWAXIDMAC_IRQ_SHADOWREG_ERR: Slave Interface shadow reg error * @DWAXIDMAC_IRQ_WRONHOLD_ERR: Slave Interface hold error * @DWAXIDMAC_IRQ_LOCK_CLEARED: Lock Cleared Status * @DWAXIDMAC_IRQ_SRC_SUSPENDED: Source Suspended Status * @DWAXIDMAC_IRQ_SUSPENDED: Channel Suspended Status * @DWAXIDMAC_IRQ_DISABLED: Channel Disabled Status * @DWAXIDMAC_IRQ_ABORTED: Channel Aborted Status * @DWAXIDMAC_IRQ_ALL_ERR: Bitmask of all error interrupts * @DWAXIDMAC_IRQ_ALL: Bitmask of all interrupts */ enum { … }; enum { … }; #endif /* _AXI_DMA_PLATFORM_H */
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