// SPDX-License-Identifier: GPL-2.0+ /* * Driver for Renesas Versaclock 3 * * Copyright (C) 2023 Renesas Electronics Corp. */ #include <linux/clk-provider.h> #include <linux/i2c.h> #include <linux/limits.h> #include <linux/module.h> #include <linux/regmap.h> #define NUM_CONFIG_REGISTERS … #define VC3_GENERAL_CTR … #define VC3_GENERAL_CTR_DIV1_SRC_SEL … #define VC3_GENERAL_CTR_PLL3_REFIN_SEL … #define VC3_PLL3_M_DIVIDER … #define VC3_PLL3_M_DIV1 … #define VC3_PLL3_M_DIV2 … #define VC3_PLL3_M_DIV(n) … #define VC3_PLL3_N_DIVIDER … #define VC3_PLL3_LOOP_FILTER_N_DIV_MSB … #define VC3_PLL3_CHARGE_PUMP_CTRL … #define VC3_PLL3_CHARGE_PUMP_CTRL_OUTDIV3_SRC_SEL … #define VC3_PLL1_CTRL_OUTDIV5 … #define VC3_PLL1_CTRL_OUTDIV5_PLL1_MDIV_DOUBLER … #define VC3_PLL1_M_DIVIDER … #define VC3_PLL1_M_DIV1 … #define VC3_PLL1_M_DIV2 … #define VC3_PLL1_M_DIV(n) … #define VC3_PLL1_VCO_N_DIVIDER … #define VC3_PLL1_LOOP_FILTER_N_DIV_MSB … #define VC3_OUT_DIV1_DIV2_CTRL … #define VC3_PLL2_FB_INT_DIV_MSB … #define VC3_PLL2_FB_INT_DIV_LSB … #define VC3_PLL2_FB_FRC_DIV_MSB … #define VC3_PLL2_FB_FRC_DIV_LSB … #define VC3_PLL2_M_DIVIDER … #define VC3_PLL2_MDIV_DOUBLER … #define VC3_PLL2_M_DIV1 … #define VC3_PLL2_M_DIV2 … #define VC3_PLL2_M_DIV(n) … #define VC3_OUT_DIV3_DIV4_CTRL … #define VC3_PLL_OP_CTRL … #define VC3_PLL_OP_CTRL_PLL2_REFIN_SEL … #define VC3_OUTPUT_CTR … #define VC3_OUTPUT_CTR_DIV4_SRC_SEL … #define VC3_SE2_CTRL_REG0 … #define VC3_SE2_CTRL_REG0_SE2_CLK_SEL … #define VC3_SE3_DIFF1_CTRL_REG … #define VC3_SE3_DIFF1_CTRL_REG_SE3_CLK_SEL … #define VC3_DIFF1_CTRL_REG … #define VC3_DIFF1_CTRL_REG_DIFF1_CLK_SEL … #define VC3_DIFF2_CTRL_REG … #define VC3_DIFF2_CTRL_REG_DIFF2_CLK_SEL … #define VC3_SE1_DIV4_CTRL … #define VC3_SE1_DIV4_CTRL_SE1_CLK_SEL … #define VC3_PLL1_VCO_MIN … #define VC3_PLL1_VCO_MAX … #define VC3_PLL2_VCO_MIN … #define VC3_PLL2_VCO_MAX … #define VC3_PLL3_VCO_MIN … #define VC3_PLL3_VCO_MAX … #define VC3_2_POW_16 … #define VC3_DIV_MASK(width) … enum vc3_pfd_mux { … }; enum vc3_pfd { … }; enum vc3_pll { … }; enum vc3_div_mux { … }; enum vc3_div { … }; enum vc3_clk { … }; enum vc3_clk_mux { … }; struct vc3_clk_data { … }; struct vc3_pfd_data { … }; struct vc3_pll_data { … }; struct vc3_div_data { … }; struct vc3_hw_data { … }; static const struct clk_div_table div1_divs[] = …; static const struct clk_div_table div245_divs[] = …; static const struct clk_div_table div3_divs[] = …; static struct clk_hw *clk_out[6]; static u8 vc3_pfd_mux_get_parent(struct clk_hw *hw) { … } static int vc3_pfd_mux_set_parent(struct clk_hw *hw, u8 index) { … } static const struct clk_ops vc3_pfd_mux_ops = …; static unsigned long vc3_pfd_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) { … } static long vc3_pfd_round_rate(struct clk_hw *hw, unsigned long rate, unsigned long *parent_rate) { … } static int vc3_pfd_set_rate(struct clk_hw *hw, unsigned long rate, unsigned long parent_rate) { … } static const struct clk_ops vc3_pfd_ops = …; static unsigned long vc3_pll_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) { … } static long vc3_pll_round_rate(struct clk_hw *hw, unsigned long rate, unsigned long *parent_rate) { … } static int vc3_pll_set_rate(struct clk_hw *hw, unsigned long rate, unsigned long parent_rate) { … } static const struct clk_ops vc3_pll_ops = …; static u8 vc3_div_mux_get_parent(struct clk_hw *hw) { … } static int vc3_div_mux_set_parent(struct clk_hw *hw, u8 index) { … } static const struct clk_ops vc3_div_mux_ops = …; static unsigned int vc3_get_div(const struct clk_div_table *table, unsigned int val, unsigned long flag) { … } static unsigned long vc3_div_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) { … } static long vc3_div_round_rate(struct clk_hw *hw, unsigned long rate, unsigned long *parent_rate) { … } static int vc3_div_set_rate(struct clk_hw *hw, unsigned long rate, unsigned long parent_rate) { … } static const struct clk_ops vc3_div_ops = …; static int vc3_clk_mux_determine_rate(struct clk_hw *hw, struct clk_rate_request *req) { … } static u8 vc3_clk_mux_get_parent(struct clk_hw *hw) { … } static int vc3_clk_mux_set_parent(struct clk_hw *hw, u8 index) { … } static const struct clk_ops vc3_clk_mux_ops = …; static const struct regmap_config vc3_regmap_config = …; static struct vc3_hw_data clk_div[5]; static const struct clk_parent_data pfd_mux_parent_data[] = …; static struct vc3_hw_data clk_pfd_mux[] = …; static struct vc3_hw_data clk_pfd[] = …; static struct vc3_hw_data clk_pll[] = …; static const struct clk_parent_data div_mux_parent_data[][2] = …; static struct vc3_hw_data clk_div_mux[] = …; static struct vc3_hw_data clk_div[] = …; static struct vc3_hw_data clk_mux[] = …; static struct clk_hw *vc3_of_clk_get(struct of_phandle_args *clkspec, void *data) { … } static int vc3_probe(struct i2c_client *client) { … } static const struct of_device_id dev_ids[] = …; MODULE_DEVICE_TABLE(of, dev_ids); static struct i2c_driver vc3_driver = …; module_i2c_driver(…) …; MODULE_AUTHOR(…) …; MODULE_DESCRIPTION(…) …; MODULE_LICENSE(…) …;
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