/* SPDX-License-Identifier: GPL-2.0-only */ /* * Header for the new SH dmaengine driver * * Copyright (C) 2010 Guennadi Liakhovetski <[email protected]> */ #ifndef SH_DMA_H #define SH_DMA_H #include <linux/dmaengine.h> #include <linux/list.h> #include <linux/shdma-base.h> #include <linux/types.h> struct device; /* Used by slave DMA clients to request DMA to/from a specific peripheral */ struct sh_dmae_slave { … }; /* * Supplied by platforms to specify, how a DMA channel has to be configured for * a certain peripheral */ struct sh_dmae_slave_config { … }; /** * struct sh_dmae_channel - DMAC channel platform data * @offset: register offset within the main IOMEM resource * @dmars: channel DMARS register offset * @chclr_offset: channel CHCLR register offset * @dmars_bit: channel DMARS field offset within the register * @chclr_bit: bit position, to be set to reset the channel */ struct sh_dmae_channel { … }; /** * struct sh_dmae_pdata - DMAC platform data * @slave: array of slaves * @slave_num: number of slaves in the above array * @channel: array of DMA channels * @channel_num: number of channels in the above array * @ts_low_shift: shift of the low part of the TS field * @ts_low_mask: low TS field mask * @ts_high_shift: additional shift of the high part of the TS field * @ts_high_mask: high TS field mask * @ts_shift: array of Transfer Size shifts, indexed by TS value * @ts_shift_num: number of shifts in the above array * @dmaor_init: DMAOR initialisation value * @chcr_offset: CHCR address offset * @chcr_ie_bit: CHCR Interrupt Enable bit * @dmaor_is_32bit: DMAOR is a 32-bit register * @needs_tend_set: the TEND register has to be set * @no_dmars: DMAC has no DMARS registers * @chclr_present: DMAC has one or several CHCLR registers * @chclr_bitwise: channel CHCLR registers are bitwise * @slave_only: DMAC cannot be used for MEMCPY */ struct sh_dmae_pdata { … }; /* DMAOR definitions */ #define DMAOR_AE … #define DMAOR_NMIF … #define DMAOR_DME … /* Definitions for the SuperH DMAC */ #define DM_INC … #define DM_DEC … #define DM_FIX … #define SM_INC … #define SM_DEC … #define SM_FIX … #define RS_AUTO … #define RS_ERS … #define CHCR_DE … #define CHCR_TE … #define CHCR_IE … #endif
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