// SPDX-License-Identifier: GPL-2.0 /* * Renesas RZ/G2L DMA Controller Driver * * Based on imx-dma.c * * Copyright (C) 2021 Renesas Electronics Corp. * Copyright 2010 Sascha Hauer, Pengutronix <[email protected]> * Copyright 2012 Javier Martin, Vista Silicon <[email protected]> */ #include <linux/bitfield.h> #include <linux/dma-mapping.h> #include <linux/dmaengine.h> #include <linux/interrupt.h> #include <linux/iopoll.h> #include <linux/list.h> #include <linux/module.h> #include <linux/of.h> #include <linux/of_dma.h> #include <linux/of_platform.h> #include <linux/platform_device.h> #include <linux/pm_runtime.h> #include <linux/reset.h> #include <linux/slab.h> #include <linux/spinlock.h> #include "../dmaengine.h" #include "../virt-dma.h" enum rz_dmac_prep_type { … }; struct rz_lmdesc { … }; struct rz_dmac_desc { … }; #define to_rz_dmac_desc(d) … struct rz_dmac_chan { … }; #define to_rz_dmac_chan(c) … struct rz_dmac { … }; #define to_rz_dmac(d) … /* * ----------------------------------------------------------------------------- * Registers */ #define CHSTAT … #define CHCTRL … #define CHCFG … #define NXLA … #define DCTRL … #define EACH_CHANNEL_OFFSET … #define CHANNEL_0_7_OFFSET … #define CHANNEL_0_7_COMMON_BASE … #define CHANNEL_8_15_OFFSET … #define CHANNEL_8_15_COMMON_BASE … #define CHSTAT_ER … #define CHSTAT_EN … #define CHCTRL_CLRINTMSK … #define CHCTRL_CLRSUS … #define CHCTRL_CLRTC … #define CHCTRL_CLREND … #define CHCTRL_CLRRQ … #define CHCTRL_SWRST … #define CHCTRL_STG … #define CHCTRL_CLREN … #define CHCTRL_SETEN … #define CHCTRL_DEFAULT … #define CHCFG_DMS … #define CHCFG_DEM … #define CHCFG_DAD … #define CHCFG_SAD … #define CHCFG_REQD … #define CHCFG_SEL(bits) … #define CHCFG_MEM_COPY … #define CHCFG_FILL_DDS_MASK … #define CHCFG_FILL_SDS_MASK … #define CHCFG_FILL_TM(a) … #define CHCFG_FILL_AM(a) … #define CHCFG_FILL_LVL(a) … #define CHCFG_FILL_HIEN(a) … #define MID_RID_MASK … #define CHCFG_MASK … #define CHCFG_DS_INVALID … #define DCTRL_LVINT … #define DCTRL_PR … #define DCTRL_DEFAULT … /* LINK MODE DESCRIPTOR */ #define HEADER_LV … #define RZ_DMAC_MAX_CHAN_DESCRIPTORS … #define RZ_DMAC_MAX_CHANNELS … #define DMAC_NR_LMDESC … /* * ----------------------------------------------------------------------------- * Device access */ static void rz_dmac_writel(struct rz_dmac *dmac, unsigned int val, unsigned int offset) { … } static void rz_dmac_ext_writel(struct rz_dmac *dmac, unsigned int val, unsigned int offset) { … } static u32 rz_dmac_ext_readl(struct rz_dmac *dmac, unsigned int offset) { … } static void rz_dmac_ch_writel(struct rz_dmac_chan *channel, unsigned int val, unsigned int offset, int which) { … } static u32 rz_dmac_ch_readl(struct rz_dmac_chan *channel, unsigned int offset, int which) { … } /* * ----------------------------------------------------------------------------- * Initialization */ static void rz_lmdesc_setup(struct rz_dmac_chan *channel, struct rz_lmdesc *lmdesc) { … } /* * ----------------------------------------------------------------------------- * Descriptors preparation */ static void rz_dmac_lmdesc_recycle(struct rz_dmac_chan *channel) { … } static void rz_dmac_enable_hw(struct rz_dmac_chan *channel) { … } static void rz_dmac_disable_hw(struct rz_dmac_chan *channel) { … } static void rz_dmac_set_dmars_register(struct rz_dmac *dmac, int nr, u32 dmars) { … } static void rz_dmac_prepare_desc_for_memcpy(struct rz_dmac_chan *channel) { … } static void rz_dmac_prepare_descs_for_slave_sg(struct rz_dmac_chan *channel) { … } static int rz_dmac_xfer_desc(struct rz_dmac_chan *chan) { … } /* * ----------------------------------------------------------------------------- * DMA engine operations */ static int rz_dmac_alloc_chan_resources(struct dma_chan *chan) { … } static void rz_dmac_free_chan_resources(struct dma_chan *chan) { … } static struct dma_async_tx_descriptor * rz_dmac_prep_dma_memcpy(struct dma_chan *chan, dma_addr_t dest, dma_addr_t src, size_t len, unsigned long flags) { … } static struct dma_async_tx_descriptor * rz_dmac_prep_slave_sg(struct dma_chan *chan, struct scatterlist *sgl, unsigned int sg_len, enum dma_transfer_direction direction, unsigned long flags, void *context) { … } static int rz_dmac_terminate_all(struct dma_chan *chan) { … } static void rz_dmac_issue_pending(struct dma_chan *chan) { … } static u8 rz_dmac_ds_to_val_mapping(enum dma_slave_buswidth ds) { … } static int rz_dmac_config(struct dma_chan *chan, struct dma_slave_config *config) { … } static void rz_dmac_virt_desc_free(struct virt_dma_desc *vd) { … } static void rz_dmac_device_synchronize(struct dma_chan *chan) { … } /* * ----------------------------------------------------------------------------- * IRQ handling */ static void rz_dmac_irq_handle_channel(struct rz_dmac_chan *channel) { … } static irqreturn_t rz_dmac_irq_handler(int irq, void *dev_id) { … } static irqreturn_t rz_dmac_irq_handler_thread(int irq, void *dev_id) { … } /* * ----------------------------------------------------------------------------- * OF xlate and channel filter */ static bool rz_dmac_chan_filter(struct dma_chan *chan, void *arg) { … } static struct dma_chan *rz_dmac_of_xlate(struct of_phandle_args *dma_spec, struct of_dma *ofdma) { … } /* * ----------------------------------------------------------------------------- * Probe and remove */ static int rz_dmac_chan_probe(struct rz_dmac *dmac, struct rz_dmac_chan *channel, u8 index) { … } static int rz_dmac_parse_of(struct device *dev, struct rz_dmac *dmac) { … } static int rz_dmac_probe(struct platform_device *pdev) { … } static void rz_dmac_remove(struct platform_device *pdev) { … } static const struct of_device_id of_rz_dmac_match[] = …; MODULE_DEVICE_TABLE(of, of_rz_dmac_match); static struct platform_driver rz_dmac_driver = …; module_platform_driver(…) …; MODULE_DESCRIPTION(…) …; MODULE_AUTHOR(…) …; MODULE_LICENSE(…) …;
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