/* SPDX-License-Identifier: GPL-2.0-or-later */ /* * TI EDMA definitions * * Copyright (C) 2006-2013 Texas Instruments. */ /* * This EDMA3 programming framework exposes two basic kinds of resource: * * Channel Triggers transfers, usually from a hardware event but * also manually or by "chaining" from DMA completions. * Each channel is coupled to a Parameter RAM (PaRAM) slot. * * Slot Each PaRAM slot holds a DMA transfer descriptor (PaRAM * "set"), source and destination addresses, a link to a * next PaRAM slot (if any), options for the transfer, and * instructions for updating those addresses. There are * more than twice as many slots as event channels. * * Each PaRAM set describes a sequence of transfers, either for one large * buffer or for several discontiguous smaller buffers. An EDMA transfer * is driven only from a channel, which performs the transfers specified * in its PaRAM slot until there are no more transfers. When that last * transfer completes, the "link" field may be used to reload the channel's * PaRAM slot with a new transfer descriptor. * * The EDMA Channel Controller (CC) maps requests from channels into physical * Transfer Controller (TC) requests when the channel triggers (by hardware * or software events, or by chaining). The two physical DMA channels provided * by the TCs are thus shared by many logical channels. * * DaVinci hardware also has a "QDMA" mechanism which is not currently * supported through this interface. (DSP firmware uses it though.) */ #ifndef EDMA_H_ #define EDMA_H_ enum dma_event_q { … }; #define EDMA_CTLR_CHAN(ctlr, chan) … #define EDMA_CTLR(i) … #define EDMA_CHAN_SLOT(i) … #define EDMA_FILTER_PARAM(ctlr, chan) … struct edma_rsv_info { … }; struct dma_slave_map; /* platform_data for EDMA driver */ struct edma_soc_info { … }; #endif
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